Feature suggestion for DGate module!

[jaffasplaffa]

Hey :)

I would like to suggest input for modulating gate time on the DGate module. You can for example use a sequencer with a row of knobs and then use the knobs for each step to set a specific gate time for each step. I think it will make sequences more interesting and "alive".

Best wishes,
Jakob

[mdemanett]

Interesting idea...I'd have to redesign it as a larger module to fit the ports, but will think about it.

Note you can do this now with DADSRH+, which has a CV-control over each stage including delay. For an alternative in less HP, you can use the AD module as a CV-controlled timer for the delay, then use its EOC (end of cycle) output to trigger another AD to produce the gate, with attack zeroed out and applying CV to the decay time.

[jaffasplaffa]

Thanks for the fast response :)

I am kind of already working on a similar module, where I think I might add that feature.

But just thought I'd suggest it anyway :)

[VegaDeftwing]

You might be able to add a switch on each of the PGMR's outputs to output as a gate length realative to the clock rate rather than the CV of the knob position. This would obviously be awkward as a step is selected manually, but even that sounds like a good feature albeit I'm not sure the best way to handle it musically.

[mdemanett]

@VegaDeftwing if I understand, you can achieve that by using a CV out from PGMR to control the decay length of an AD, where AD is triggered by the clock, and it's out is used as the gate?

[VegaDeftwing]

Sort of. That makes it so the delay length is set directly by the knob position instead of as a division of clock timing, making it so that adjusting the clock rate changes the realative gate width. This can easily result in turning the clock fast enough that a previously square wave turns into a DC offset.

I hope that makes sense?

[mdemanett]

Oh, yep, that makes sense. Maybe there should be a module for that (and probably there is already, in some other collection) -- that takes a clock, has a gate length knob and CV, and outputs a clock-relative gate. ARP actually does this, but without a gate length CV.

[VegaDeftwing]

At least as far as I could tell there's nothing that serves the purpose well, at least no clean, single module solution.

…

On Mon, Aug 10, 2020, 9:55 PM Matt Demanett ***@***.***> wrote: Oh, yep, that makes sense. Maybe there should be a module for that (and probably there is already, in some other collection) -- that takes a clock, has a gate length knob and CV, and outputs a clock-relative gate. ARP actually does this, but without a gate length CV. — You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub <#129 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/ACWCZJCHK4CKIPWUVS5W75TSACXJNANCNFSM4PIXAD3Q> .

[VegaDeftwing]

This was about as close as I could get.

[mdemanett]

Cool, I'll look into making something.

[VegaDeftwing]

Sweet. Also, I realize it's a separate issue, but if this is potentially going to require a redesign of PGMR's panel to some extent anyway: It'd be nice to have CV control over the forward/reverse switch and/or phase based clocking to provide the same functionality- I can open a separate issue for that if you like

[mdemanett]

You can use a negative clock pulse -- see the documentation for 8:1, the bit about option "Reverse step on negative clock". Turn that on and process the clock with INV, which is a CV-controlled inverter.

[mdemanett]

So I went ahead and made a clock relative gate utility, RGATE. It also divide/multiply a clock. In the new build here.

An inherent difficulty with this sort of thing is that you really need to have seen two clock pulses to know the clock period, to set the output gate length. So it outputs a fixed gate on the first clock received, which is modestly customizable on the context menu.

Then, if you use a steady clock, all should be peachy. An irregular clock will have odd effects. Starting and stopping the clock complicates things...to deal with that, I put in a RUN port and way too many context menu options about what it does.

Real documentation will be forthcoming when this releases for real; for now here's a sample patch. The first four steps from PGMR vary the gate length, and the last four use the multiplier to do ratchets. Also it starts and stops with the clock.

rgate.vcv.zip

[VegaDeftwing]

It's nearly 1am here, so I can't test it now; however, this looks absolutely amazing! I'm really looking forward to trying it out tomorrow!

[VegaDeftwing]

Got a chance to test it out, first just checked for bugs- seems to work impressively well, actually working as a pretty interesting sub-octave generator with pwm capabilities when fed a square wave osc. Otherwise, for it's normal use case it worked pretty much exactly as expected and was a heck of a lot of fun.

[mdemanett]

Nice, thanks for giving it a whirl!

[mdemanett]

RGATE is in the new release available on the library.