Merge of v4 into master; future development to happen from this model

attribs

@@ -1,3 +1,5 @@
 device
 value
 footprint
+digikey
+price

board.cmd

@@ -1,37 +1,75 @@
 # Pin name action command file
 
+# Start of element C4
+ChangePinName(C4, 2, 2)
+ChangePinName(C4, 1, 1)
+
+# Start of element R4
+ChangePinName(R4, 1, 1)
+ChangePinName(R4, 2, 2)
+
+# Start of element Q1
+ChangePinName(Q1, 3, G)
+ChangePinName(Q1, 2, S)
+ChangePinName(Q1, 1, D)
+
+# Start of element V2
+ChangePinName(V2, 2, 2)
+ChangePinName(V2, 1, 1)
+
+# Start of element V1
+ChangePinName(V1, 2, 2)
+ChangePinName(V1, 1, 1)
+
 # Start of element D1
 ChangePinName(D1, 2, 2)
 ChangePinName(D1, 1, 1)
 
+# Start of element R3
+ChangePinName(R3, 1, 1)
+ChangePinName(R3, 2, 2)
+
+# Start of element B1
+ChangePinName(B1, 2, -)
+ChangePinName(B1, 1, +)
+
+# Start of element C3
+ChangePinName(C3, 2, 2)
+ChangePinName(C3, 1, 1)
+
+# Start of element C1
+ChangePinName(C1, 2, 2)
+ChangePinName(C1, 1, 1)
+
+# Start of element C2
+ChangePinName(C2, 2, 2)
+ChangePinName(C2, 1, 1)
+
+# Start of element CONN1
+ChangePinName(CONN1, 1, 1)
+ChangePinName(CONN1, 2, 2)
+
+# Start of element U2
+ChangePinName(U2, 1, C1-)
+ChangePinName(U2, 2, C2+)
+ChangePinName(U2, 3, C2-)
+ChangePinName(U2, 4, -Vout)
+ChangePinName(U2, 5, GND)
+ChangePinName(U2, 6, Vin)
+ChangePinName(U2, 7, C1+)
+ChangePinName(U2, 8, +Vout)
+
 # Start of element R1
+ChangePinName(R1, 1, 1)
+ChangePinName(R1, 3, 3)
 ChangePinName(R1, 2, 2)
 ChangePinName(R1, 1, 1)
 
 # Start of element R2
 ChangePinName(R2, 1, 1)
 ChangePinName(R2, 2, 2)
 
-# Start of element V1
-ChangePinName(V1, 2, -)
-ChangePinName(V1, 1, +)
-
 # Start of element U1
 ChangePinName(U1, 1, V+)
 ChangePinName(U1, 2, R)
 ChangePinName(U1, 3, V-)
-
-# Start of element R3
-ChangePinName(R3, 1, 1)
-ChangePinName(R3, 3, 3)
-ChangePinName(R3, 2, 2)
-
-# Start of element Anode
-ChangePinName(Anode, 1, terminal)
-
-# Start of element Cathode
-ChangePinName(Cathode, 1, terminal)
-
-# Start of element C1
-ChangePinName(C1, 2, 2)
-ChangePinName(C1, 1, 1)

board.net

@@ -1,6 +1,14 @@
-unnamed_net6	D1-1 R1-2 
-unnamed_net5	R1-1 V1-1 U1-1 
-unnamed_net4	R2-2 U1-2 
-unnamed_net3	R2-1 R3-1 
-unnamed_net2	V1-2 D1-2 Cathode-1 C1-2 
-unnamed_net1	U1-3 R3-2 Anode-1 C1-1 
+unnamed_net12	R4-1 Q1-2 
+unnamed_net11	D1-1 R3-1 
+unnamed_net10	Q1-3 R4-2 V2-1 CONN1-1 
+unnamed_net9	C1-2 U2-1 
+unnamed_net8	C3-2 U2-2 
+unnamed_net7	C3-1 U2-3 
+unnamed_net6	C4-2 Q1-1 U2-4 
+GND	C4-1 V2-2 V1-2 D1-2 B1-2 C2-2 U2-5 
+Vcc	R3-2 B1-1 U2-6 
+unnamed_net5	C1-1 U2-7 
+unnamed_net4	R1-2 R2-2 
+unnamed_net3	C2-1 U2-8 U1-1 
+unnamed_net2	R2-1 U1-2 
+unnamed_net1	V1-1 CONN1-2 R1-1 U1-3