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1. update user_subsys and connect to user project 0
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2. user project support axilite read/write and axis loopback
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@TonyHo722
TonyHo722 committed Sep 29, 2023
1 parent cbf2918 commit 093da0d
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203 changes: 161 additions & 42 deletions rtl/user/user_subsys/rtl/user_subsys.all.v
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Expand Up @@ -67,32 +67,92 @@ module AXIL_SLAV #( parameter pADDR_WIDTH = 12,
input wire [4: 0] user_prj_sel
);

wire [3:0] axi_awready_bus;
assign axi_awready = |axi_awready_bus;

assign awvalid_0 = 1'b0;
assign awaddr = 12'b0;
assign arvalid_0 = 1'b0;
assign araddr = 12'b0;
assign wvalid_0 = 1'b0;
assign wstrb_0 = 4'b0;
assign wdata = {pDATA_WIDTH{1'b0}};
assign rready = 1'b0;
assign awvalid_1 = 1'b0;
assign arvalid_1 = 1'b0;
assign wvalid_1 = 1'b0;
assign wstrb_1 = 4'b0;
assign awvalid_2 = 1'b0;
assign arvalid_2 = 1'b0;
assign wvalid_2 = 1'b0;
assign wstrb_2 = 4'b0;
assign awvalid_3 = 1'b0;
assign arvalid_3 = 1'b0;
assign wvalid_3 = 1'b0;
assign wstrb_3 = 4'b0;
assign axi_awready = 1'b0;
assign axi_arready = 1'b0;
assign axi_wready = 1'b0;
assign axi_rvalid = 1'b0;
assign axi_rdata = {pDATA_WIDTH{1'b0}};
wire [3:0] axi_wready_bus;
assign axi_wready = |axi_wready_bus;

wire [3:0] axi_arready_bus;
assign axi_arready = |axi_arready_bus;

wire [3:0] axi_rvalid_bus;
assign axi_rvalid = |axi_rvalid_bus;

wire [(pDATA_WIDTH-1) : 0] axi_rdata_bus[3:0];
assign axi_rdata = axi_rdata_bus[0] | axi_rdata_bus[1] | axi_rdata_bus[2] | axi_rdata_bus[3];

//user project 0
assign awvalid_0 = ( (user_prj_sel == 5'b00000) && cc_up_enable) ? axi_awvalid : 0;
assign axi_awready_bus[0] = ( (user_prj_sel == 5'b00000) && cc_up_enable) ? awready_0 : 0;
assign awaddr = axi_awaddr[11:0];
assign wstrb_0 = axi_wstrb; //[TODO] share wstrb for all user projects.

assign wvalid_0 = ( (user_prj_sel == 5'b00000) && cc_up_enable) ? axi_wvalid : 0;
assign axi_wready_bus[0] = ( (user_prj_sel == 5'b00000) && cc_up_enable) ? wready_0 : 0;
assign wdata = axi_wdata;

assign arvalid_0 = ( (user_prj_sel == 5'b00000) && cc_up_enable) ? axi_arvalid : 0;
assign axi_arready_bus[0] = ( (user_prj_sel == 5'b00000) && cc_up_enable) ? arready_0 : 0;
assign araddr = axi_araddr;

assign axi_rvalid_bus[0] = ( (user_prj_sel == 5'b00000) && cc_up_enable) ? rvalid_0 : 0;
assign rready = axi_rready;
assign axi_rdata_bus[0] = ( (user_prj_sel == 5'b00000) && cc_up_enable) ? rdata_0 : 0;

//user project 1
assign awvalid_1 = ( (user_prj_sel == 5'b00001) && cc_up_enable) ? axi_awvalid : 0;
assign axi_awready_bus[1] = ( (user_prj_sel == 5'b00001) && cc_up_enable) ? awready_0 : 0;
assign awaddr = axi_awaddr[11:0];
assign wstrb_1 = axi_wstrb; //[TODO] share wstrb for all user projects.

assign wvalid_1 = ( (user_prj_sel == 5'b00001) && cc_up_enable) ? axi_wvalid : 0;
assign axi_wready_bus[1] = ( (user_prj_sel == 5'b00001) && cc_up_enable) ? wready_0 : 0;
assign wdata = axi_wdata;

assign arvalid_1 = ( (user_prj_sel == 5'b00001) && cc_up_enable) ? axi_arvalid : 0;
assign axi_arready_bus[1] = ( (user_prj_sel == 5'b00001) && cc_up_enable) ? arready_0 : 0;
assign araddr = axi_araddr;

assign axi_rvalid_bus[1] = ( (user_prj_sel == 5'b00001) && cc_up_enable) ? rvalid_0 : 0;
assign rready = axi_rready;
assign axi_rdata_bus[1] = ( (user_prj_sel == 5'b00001) && cc_up_enable) ? rdata_0 : 0;

//user project 2
assign awvalid_2 = ( (user_prj_sel == 5'b00010) && cc_up_enable) ? axi_awvalid : 0;
assign axi_awready_bus[2] = ( (user_prj_sel == 5'b00010) && cc_up_enable) ? awready_0 : 0;
assign awaddr = axi_awaddr[11:0];
assign wstrb_2 = axi_wstrb; //[TODO] share wstrb for all user projects.

assign wvalid_2 = ( (user_prj_sel == 5'b00010) && cc_up_enable) ? axi_wvalid : 0;
assign axi_wready_bus[2] = ( (user_prj_sel == 5'b00010) && cc_up_enable) ? wready_0 : 0;
assign wdata = axi_wdata;

assign arvalid_2 = ( (user_prj_sel == 5'b00010) && cc_up_enable) ? axi_arvalid : 0;
assign axi_arready_bus[2] = ( (user_prj_sel == 5'b00010) && cc_up_enable) ? arready_0 : 0;
assign araddr = axi_araddr;

assign axi_rvalid_bus[2] = ( (user_prj_sel == 5'b00010) && cc_up_enable) ? rvalid_0 : 0;
assign rready = axi_rready;
assign axi_rdata_bus[2] = ( (user_prj_sel == 5'b00010) && cc_up_enable) ? rdata_0 : 0;

//user project 3
assign awvalid_3 = ( (user_prj_sel == 5'b00011) && cc_up_enable) ? axi_awvalid : 0;
assign axi_awready_bus[3] = ( (user_prj_sel == 5'b00011) && cc_up_enable) ? awready_0 : 0;
assign awaddr = axi_awaddr[11:0];
assign wstrb_3 = axi_wstrb; //[TODO] share wstrb for all user projects.

assign wvalid_3 = ( (user_prj_sel == 5'b00011) && cc_up_enable) ? axi_wvalid : 0;
assign axi_wready_bus[3] = ( (user_prj_sel == 5'b00011) && cc_up_enable) ? wready_0 : 0;
assign wdata = axi_wdata;

assign arvalid_3 = ( (user_prj_sel == 5'b00011) && cc_up_enable) ? axi_arvalid : 0;
assign axi_arready_bus[3] = ( (user_prj_sel == 5'b00011) && cc_up_enable) ? arready_0 : 0;
assign araddr = axi_araddr;

assign axi_rvalid_bus[3] = ( (user_prj_sel == 5'b00011) && cc_up_enable) ? rvalid_0 : 0;
assign rready = axi_rready;
assign axi_rdata_bus[3] = ( (user_prj_sel == 5'b00011) && cc_up_enable) ? rdata_0 : 0;


endmodule // AXIL_SLAV
Expand Down Expand Up @@ -144,14 +204,56 @@ module AXIS_MSTR #( parameter pADDR_WIDTH = 12,
input wire [4: 0] user_prj_sel
);

//common part
assign sm_tready = m_tready;

//bus
wire [3:0] sm_tvalid_bus;
assign m_tvalid = |sm_tvalid_bus;

wire [(pDATA_WIDTH-1) : 0] sm_tdata_bus[3:0];
assign m_tdata = sm_tdata_bus[0] | sm_tdata_bus[1] | sm_tdata_bus[2] | sm_tdata_bus[3];

//wire [2: 0] sm_tid_bus;

wire [3: 0] sm_tstrb_bus[3:0];
assign m_tstrb = sm_tstrb_bus[0] | sm_tstrb_bus[1] | sm_tstrb_bus[2] | sm_tstrb_bus[3];

wire [3: 0] sm_tkeep_bus[3:0];
assign m_tkeep = sm_tkeep_bus[0] | sm_tkeep_bus[1] | sm_tkeep_bus[2] | sm_tkeep_bus[3];

wire [3: 0] sm_tlast_bus[3:0];
assign m_tlast = sm_tlast_bus[0] | sm_tlast_bus[1] | sm_tlast_bus[2] | sm_tlast_bus[3];

//user project 0
assign sm_tvalid_bus[0] = (user_prj_sel == 5'b00000) ? sm_tvalid_0 : 0;
assign sm_tdata_bus[0] = (user_prj_sel == 5'b00000) ? sm_tdata_0 : 0;
assign sm_tstrb_bus[0] = (user_prj_sel == 5'b00000) ? sm_tstrb_0 : 0;
assign sm_tkeep_bus[0] = (user_prj_sel == 5'b00000) ? sm_tkeep_0 : 0;
assign sm_tlast_bus[0] = (user_prj_sel == 5'b00000) ? sm_tlast_0 : 0;

//user project 1
assign sm_tvalid_bus[1] = (user_prj_sel == 5'b00001) ? sm_tvalid_1 : 0;
assign sm_tdata_bus[1] = (user_prj_sel == 5'b00001) ? sm_tdata_1 : 0;
assign sm_tstrb_bus[1] = (user_prj_sel == 5'b00001) ? sm_tstrb_1 : 0;
assign sm_tkeep_bus[1] = (user_prj_sel == 5'b00001) ? sm_tkeep_1 : 0;
assign sm_tlast_bus[1] = (user_prj_sel == 5'b00001) ? sm_tlast_1 : 0;

assign sm_tready = 1'b0;
assign m_tvalid = 1'b0;
assign m_tdata = {pDATA_WIDTH{1'b0}};
assign m_tuser = 2'b0;
assign m_tstrb = 4'b0;
assign m_tkeep = 4'b0;
assign m_tlast = 1'b0;
//user project 2
assign sm_tvalid_bus[2] = (user_prj_sel == 5'b00010) ? sm_tvalid_2 : 0;
assign sm_tdata_bus[2] = (user_prj_sel == 5'b00010) ? sm_tdata_2 : 0;
assign sm_tstrb_bus[2] = (user_prj_sel == 5'b00010) ? sm_tstrb_2 : 0;
assign sm_tkeep_bus[2] = (user_prj_sel == 5'b00010) ? sm_tkeep_2 : 0;
assign sm_tlast_bus[2] = (user_prj_sel == 5'b00010) ? sm_tlast_2 : 0;

//user project 3
assign sm_tvalid_bus[3] = (user_prj_sel == 5'b00011) ? sm_tvalid_3 : 0;
assign sm_tdata_bus[3] = (user_prj_sel == 5'b00011) ? sm_tdata_3 : 0;
assign sm_tstrb_bus[3] = (user_prj_sel == 5'b00011) ? sm_tstrb_3 : 0;
assign sm_tkeep_bus[3] = (user_prj_sel == 5'b00011) ? sm_tkeep_3 : 0;
assign sm_tlast_bus[3] = (user_prj_sel == 5'b00011) ? sm_tlast_3 : 0;

assign m_tuser = 2'b00; //MUST be 2'b00 for user project output axis from UP to AS.


endmodule // AXIS_MSTR
Expand Down Expand Up @@ -191,17 +293,33 @@ module AXIS_SLAV #( parameter pADDR_WIDTH = 12,
input wire [4: 0] user_prj_sel
);

//common part
assign ss_tdata = s_tdata;
assign ss_tuser = 2'b00; //UP always received tuser = 2'b00, the tuser is used by AS, should not send to UP.
assign ss_tstrb = s_tstrb;
assign ss_tkeep = s_tkeep;
assign ss_tlast = s_tlast;

wire [3:0] s_tready_bus;
assign s_tready = |s_tready_bus;

//user project 0
assign ss_tvalid_0 = (user_prj_sel == 5'b00000) ? s_tvalid : 0;
assign s_tready_bus[0] = (user_prj_sel == 5'b00000) ? ss_tready_0 : 0;

//user project 1
assign ss_tvalid_1 = (user_prj_sel == 5'b00001) ? s_tvalid : 0;
assign s_tready_bus[1] = (user_prj_sel == 5'b00001) ? ss_tready_1 : 0;

//user project 2
assign ss_tvalid_2 = (user_prj_sel == 5'b00010) ? s_tvalid : 0;
assign s_tready_bus[2] = (user_prj_sel == 5'b00010) ? ss_tready_2 : 0;

//user project 3
assign ss_tvalid_3 = (user_prj_sel == 5'b00011) ? s_tvalid : 0;
assign s_tready_bus[3] = (user_prj_sel == 5'b00011) ? ss_tready_3 : 0;


assign ss_tvalid_0 = 1'b0;
assign ss_tdata = {pDATA_WIDTH{1'b0}};
assign ss_tuser = 2'b0;
assign ss_tstrb = 4'b0;
assign ss_tkeep = 4'b0;
assign ss_tlast = 1'b0;
assign ss_tvalid_1 = 1'b0;
assign ss_tvalid_2 = 1'b0;
assign ss_tvalid_3 = 1'b0;
assign s_tready = 1'b0;


endmodule // AXIS_SLAV
Expand Down Expand Up @@ -794,3 +912,4 @@ LA_MUX #(.pADDR_WIDTH( 12 ),


endmodule // USER_SUBSYS

99 changes: 87 additions & 12 deletions rtl/user/user_subsys/user_prj/rtl/user_prj0.v
View file
Expand Up @@ -46,22 +46,97 @@ module USER_PRJ0 #( parameter pADDR_WIDTH = 12,
input wire uck2_rst_n
);

localparam FIFO_WIDTH = 4 + 1 + 1 + pDATA_WIDTH; //tid, tstrb, tkeep, tlast, tdata

assign awready = 1'b0;
assign arready = 1'b0;
assign wready = 1'b0;
assign rvalid = 1'b0;
assign rdata = {pDATA_WIDTH{1'b0}};
assign ss_tready = 1'b0;
assign sm_tvalid = 1'b0;
assign sm_tdata = {pDATA_WIDTH{1'b0}};
assign sm_tid = 3'b0;
assign sm_tstrb = 4'b0;
assign sm_tkeep = 1'b0;
assign sm_tlast = 1'b0;
wire awvalid_in;
wire wvalid_in;

reg [31:0] RegisterData;

//write addr channel
assign awvalid_in = awvalid;
wire awready_out;
assign awready = awready_out;

//write data channel
assign wvalid_in = wvalid;
wire wready_out;
assign wready = wready_out;

// if both awvalid_in=1 and wvalid_in=1 then output awready_out = 1 and wready_out = 1
assign awready_out = (awvalid_in && wvalid_in) ? 1 : 0;
assign wready_out = (awvalid_in && wvalid_in) ? 1 : 0;

assign arready = 1;

assign rvalid = 1;
assign rdata = RegisterData;

//write register
always @(posedge axi_clk or negedge axi_reset_n) begin
if ( !axi_reset_n ) begin
RegisterData <= 32'haa55aa55;
end
else begin
if ( awvalid_in && wvalid_in ) begin //when awvalid_in=1 and wvalid_in=1 means awready_out=1 and wready_out=1
if (awaddr[11:2] == 10'h000 ) begin //offset 0
if ( wstrb[0] == 1) RegisterData[7:0] <= wdata[7:0];
if ( wstrb[1] == 1) RegisterData[15:8] <= wdata[15:8];
if ( wstrb[2] == 1) RegisterData[23:16] <= wdata[23:16];
if ( wstrb[3] == 1) RegisterData[31:24] <= wdata[31:24];
end
else begin
RegisterData <= RegisterData;
end
end
end
end

reg [2:0] r_ptr;
reg [2:0] w_ptr;
reg [(FIFO_WIDTH-1) : 0] fifo[7:0];

wire full;
wire empty;

assign empty = (r_ptr == w_ptr);
assign full = (r_ptr == (w_ptr+1) );

assign ss_tready = !full;

//for push to fifo
always @(posedge axis_clk or negedge axis_rst_n) begin
if ( !axis_rst_n ) begin
w_ptr <= 0;
end
else begin
if ( ss_tready && ss_tvalid) begin
fifo[w_ptr] <= {ss_tstrb, ss_tkeep, ss_tlast, ss_tdata};
w_ptr <= w_ptr + 1;
end
end
end

//for pop from fifo
assign {sm_tstrb, sm_tkeep, sm_tlast, sm_tdata} = fifo[r_ptr];
assign sm_tvalid = !empty;
always @(posedge axis_clk or negedge axis_rst_n) begin
if ( !axis_rst_n ) begin
r_ptr <= 0;
end
else begin
if ( sm_tready && sm_tvalid) begin
r_ptr <= r_ptr + 1;
end
end
end

assign sm_tid = 3'b000; //[TODO] remove tid in user project.
assign low__pri_irq = 1'b0;
assign High_pri_req = 1'b0;
assign la_data_o = 24'b0;


endmodule // USER_PRJ0


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