/
bonfire-basic-soc.core
188 lines (168 loc) · 3.81 KB
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bonfire-basic-soc.core
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CAPI=2:
name: ::bonfire-basic-soc:0
filesets:
code:
file_type: user
files:
- compiled_code/sim_hello.hex
gpio_sim:
file_type: vhdlSource
files:
- tb/gpio_pad_sim.vhd
gpio_xilinx:
file_type: vhdlSource
files:
- gpio_pad.vhd
rtl:
depend:
- ::bonfire-cpu:0
- ::bonfire-util:0
- '>=::bonfire-soc-io:0'
- '>=::bonfire-dcache:0'
file_type: vhdlSource-2008
files:
- MainMemory.vhd
- memory/ram8.vhd
- memory/main_memory_laned.vhd
- cpu_dbus_connect.vhd
- dram_arbiter.vhd
- bonfire_basic_soc.vhd
- bonfire_basic_soc_top.vhd
sim:
file_type: vhdlSource
files:
- tb/tb_bonfire_basic_soc.vhd
- tb/clkgen_sim.vhd
vivado_ip:
file_type: xci
files:
- vivado/clkgen_arty.xci
xdc:
file_type: xdc
files:
- Arty.xdc
xdc_cmods7:
file_type: xdc
files:
- cmods7/cmod.xdc
cmods7_files:
file_type: vhdlSource-2008
files:
- cmods7/cmods7_top.vhd
ulx3s_files:
file_type: vhdlSource-2008
files:
- ulx3s/soc_ulx3s_top.vhd
- ulx3s/clock_gen.vhd
- ulx3s/ecp_mult33.vhd
- tb/gpio_pad_sim.vhd
- sdram/wbs_sdram_interface.vhd
- sdram/SDRAM_Controller.vhd
lpf:
file_type: LPF
files:
- ulx3s/ulx3s_v20.lpf
# sbx:
# file_type: SBX
# files:
# - ulx3s/diamond/ecp_mult33.sbx
parameters:
BRAM_ADR_WIDTH:
datatype : int
default : '12'
description: "BRAM Adress width"
paramtype: generic
RamFileName:
#datatype: file
datatype: str
default: compiled_code/sim_hello.hex
description: Initial boot RAM contents (in hex)
paramtype: generic
CLK_FREQ_MHZ:
datatype: int
default: 12
description: Cock frequency in Mhz
paramtype: generic
Swapbytes:
datatype: bool
default: false
paramtype: generic
UART_BAUDRATE:
datatype: int
default: 38400
paramtype: generic
M_EXTENSION:
datatype: str
default: true
paramtype: generic
description: Enable M Extension
BRANCH_PREDICTOR:
datatype: str
default: true
paramtype: generic
description: Enable Branch Predictor
DEVICE_FAMILY:
datatype: str
default: ""
paramtype: generic
description: "Enable device specific synthesis options, currently ECP5 and SPARTAN6 supported"
USE_BONFIRE_CORE:
datatype: str
default: false
paramtype: generic
description: Need to stay false for this core !!!
targets:
default:
filesets:
- rtl
sim:
default_tool: ghdl
filesets:
- code
- gpio_sim
- rtl
- sim
parameters: [ BRAM_ADR_WIDTH, RamFileName, CLK_FREQ_MHZ, UART_BAUDRATE, USE_BONFIRE_CORE, M_EXTENSION, BRANCH_PREDICTOR, DEVICE_FAMILY ]
tools:
ghdl:
analyze_options: [--ieee=synopsys, -frelaxed-rules ]
run_options: [ --ieee-asserts=disable, --max-stack-alloc=0 ] ## --wave=soc.ghw, --stop-time=3000000ns ]
xsim:
xelab_options: [ "--debug typical" ]
toplevel: tb_bonfire_basic_soc
synth:
default_tool: vivado
filesets:
- gpio_xilinx
- rtl
- xdc
- vivado_ip
tools:
vivado:
part: xc7a35ticsg324-1L
toplevel:
- bonfire_basic_soc_top
synth-cmods7:
default_tool: vivado
parameters: [ BRAM_ADR_WIDTH, RamFileName ]
filesets:
- gpio_xilinx
- rtl
- cmods7_files
- xdc_cmods7
tools:
vivado:
board_part: DIGILENTINC.COM:CMOD-S7-25:PART0:1.0
toplevel:
- cmod_s7_top
synth-ulx3s:
default_tool: diamond
#parameters: [ RamFileName, USE_BONFIRE_CORE ]
filesets:
- ulx3s_files
- rtl
- lpf
tools:
diamond:
part: LFE5U-85F-6BG381C
toplevel: soc_ulx3s_top