Pinned repositories

  1. bonfire-cpu

    Forked from lxp32/lxp32-cpu

    FPGA optimized RISC-V (RV32IM) implemenation

    VHDL 6 1

  2. bonfire-basic-soc

    Simple SOC which uses only internal FPGA ressources and can be synthesized and simulated easily

    VHDL

  3. bonfire_arty_a7_full

    Bonfire implementation for Digilent Arty board with Network and DRAM

    Tcl

  • HTML Updated Jul 27, 2018
  • Bonfire toplevel with AXI4 Interfaces

    VHDL MIT Updated Jul 25, 2018
  • Root repository, contains everything else as submodules

    Updated Jul 23, 2018
  • gdb-proxy implementation for bonfire

    C MIT Updated Jul 22, 2018
  • VHDL MIT Updated Jul 22, 2018
  • IO block of bonfire-soc

    VHDL MIT Updated Jul 22, 2018
  • C Updated Jul 21, 2018
  • VHDL MIT Updated Jul 21, 2018
  • GPIO core for bonfire

    VHDL MIT Updated Jul 21, 2018
  • FPGA optimized RISC-V (RV32IM) implemenation

    VHDL 6 5 Updated Jul 21, 2018
  • Test and example for xpack bsp

    C MIT Updated Jul 17, 2018
  • Bonfire BSP Arty xPack

    C++ MIT Updated Jul 15, 2018
  • Bonfire implementation for Digilent Arty board with Network and DRAM

    Tcl MIT Updated Jul 12, 2018
  • VHDL Updated Jun 6, 2018
  • Simple SOC which uses only internal FPGA ressources and can be synthesized and simulated easily

    VHDL Updated May 10, 2018
  • AXI4Lite to Wishbone Bridge

    VHDL MIT Updated Apr 25, 2018
  • VHDL GPL-3.0 Updated Mar 31, 2018
  • VHDL 2 GPL-3.0 Updated Mar 31, 2018
  • Various dockerfiles for Bonfire build configurations

    MIT Updated Jan 14, 2018
  • Updated Dec 15, 2016
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