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Merge pull request boriel-basic#576 from boriel/bugfix/allow_brackets…
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…_for_16bit_regs

fix: allow ld [NNNN], reg16
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boriel committed Oct 13, 2021
2 parents 7d0429f + 4b8a4ce commit 1a6aacc
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Showing 6 changed files with 21 additions and 8 deletions.
6 changes: 3 additions & 3 deletions src/parsetab/tabs.dbm.bak
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
'zxbpp', (0, 76970)
'asmparse', (77312, 268394)
'zxnext_asmparse', (346112, 298411)
'zxbparser', (644608, 704752)
'asmparse', (77312, 268610)
'zxnext_asmparse', (346112, 298625)
'zxbparser', (645120, 704752)
Binary file modified src/parsetab/tabs.dbm.dat
Binary file not shown.
6 changes: 3 additions & 3 deletions src/parsetab/tabs.dbm.dir
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
'zxbpp', (0, 76970)
'asmparse', (77312, 268394)
'zxnext_asmparse', (346112, 298411)
'zxbparser', (644608, 704752)
'asmparse', (77312, 268610)
'zxnext_asmparse', (346112, 298625)
'zxbparser', (645120, 704752)
4 changes: 2 additions & 2 deletions src/zxbasm/asmparse.py
Original file line number Diff line number Diff line change
Expand Up @@ -552,8 +552,8 @@ def p_LD_addr_reg(p): # Load address,reg
| LD pexpr COMMA reg16
| LD pexpr COMMA SP
| LD mem_indir COMMA A
| LD mem_indir reg16
| LD mem_indir SP
| LD mem_indir COMMA reg16
| LD mem_indir COMMA SP
"""
p[0] = Asm(p.lineno(1), "LD (NN),%s" % p[4], p[2])

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12 changes: 12 additions & 0 deletions tests/functional/ld_hl16_bracket.asm
Original file line number Diff line number Diff line change
@@ -0,0 +1,12 @@

ld (0x1234), hl
ld [0x1234], hl

ld (0x1234), bc
ld [0x1234], bc

ld [0x1234], de
ld (0x1234), de

ld (0x1234), sp
ld [0x1234], sp
1 change: 1 addition & 0 deletions tests/functional/ld_hl16_bracket.bin
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
"4"4�C4�C4�S4�S4�s4�s4

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