add muldiv_inst to pipeline register(s)

bwalex · Jul 29, 2012 · a21b863 · a21b863
1 parent 20853a0
commit a21b863
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diff --git a/hdl/pipreg_id_ex.sv b/hdl/pipreg_id_ex.sv
@@ -25,6 +25,7 @@ module pipreg_id_ex(
   input alu_op_t id_alu_op,
   input alu_res_t id_alu_res_sel,
   input [0:0] id_alu_set_u,
+  input [0:0] id_muldiv_inst,
   input muldiv_op_t id_muldiv_op,
   input [0:0] id_muldiv_op_u,
   input ls_op_t id_ls_op,
@@ -59,6 +60,7 @@ module pipreg_id_ex(
   output alu_op_t ex_alu_op,
   output alu_res_t ex_alu_res_sel,
   output reg [0:0] ex_alu_set_u,
+  output reg [0:0] ex_muldiv_inst,
   output muldiv_op_t ex_muldiv_op,
   output reg [0:0] ex_muldiv_op_u,
   output ls_op_t ex_ls_op,
@@ -100,6 +102,7 @@ module pipreg_id_ex(
       ex_alu_op<= OP_PASS_A;
       ex_alu_res_sel<= RES_ALU;
       ex_alu_set_u<= 'b0;
+      ex_muldiv_inst<= 'b0;
       ex_muldiv_op<= OP_NONE;
       ex_muldiv_op_u<= 'b0;
       ex_ls_op<= OP_LS_WORD;
@@ -135,6 +138,7 @@ module pipreg_id_ex(
       ex_alu_op <= id_alu_op;
       ex_alu_res_sel <= id_alu_res_sel;
       ex_alu_set_u <= id_alu_set_u;
+      ex_muldiv_inst <= id_muldiv_inst;
       ex_muldiv_op <= id_muldiv_op;
       ex_muldiv_op_u <= id_muldiv_op_u;
       ex_ls_op <= id_ls_op;

diff --git a/tools/pipeline_regs.yml b/tools/pipeline_regs.yml
@@ -25,6 +25,7 @@ ID_EX:
  - alu_op/alu_op_t/OP_PASS_A
  - alu_res_sel/alu_res_t/RES_ALU
  - alu_set_u/1
+ - muldiv_inst/1
  - muldiv_op/muldiv_op_t/OP_NONE
  - muldiv_op_u/1
  - ls_op/ls_op_t/OP_LS_WORD