[WIP]

cranelift-codegen/meta-python/base/instructions.py

@@ -2012,7 +2012,7 @@
 
 WideInt = TypeVar(
         'WideInt', 'An integer type with lanes from `i16` upwards',
-        ints=(16, 64), simd=True)
+        ints=(16, 128), simd=True)
 x = Operand('x', WideInt)
 lo = Operand(
         'lo', WideInt.half_width(), 'The low bits of `x`')
@@ -2033,8 +2033,8 @@
 
 
 NarrowInt = TypeVar(
-        'NarrowInt', 'An integer type with lanes type to `i32`',
-        ints=(8, 32), simd=True)
+        'NarrowInt', 'An integer type with lanes type to `i64`',
+        ints=(8, 64), simd=True)
 lo = Operand('lo', NarrowInt)
 hi = Operand('hi', NarrowInt)
 a = Operand(

cranelift-codegen/src/ir/types.rs

@@ -10,7 +10,7 @@ use target_lexicon::{PointerWidth, Triple};
 /// field is present put no type is needed, such as the controlling type variable for a
 /// non-polymorphic instruction.
 ///
-/// Basic integer types: `I8`, `I16`, `I32`, and `I64`. These types are sign-agnostic.
+/// Basic integer types: `I8`, `I16`, `I32`, `I64`, and `I128`. These types are sign-agnostic.
 ///
 /// Basic floating point types: `F32` and `F64`. IEEE single and double precision.
 ///

cranelift-codegen/src/legalizer/mod.rs

@@ -56,6 +56,35 @@ fn legalize_inst(
         }
     } else if opcode.is_branch() {
         split::simplify_branch_arguments(&mut pos.func.dfg, inst);
+    } else if opcode == ir::Opcode::Isplit {
+        dbg!(());
+        pos.use_srcloc(inst);
+
+        let arg = match pos.func.dfg[inst] {
+            ir::InstructionData::Unary {
+                arg,
+                ..
+            } => pos.func.dfg.resolve_aliases(arg),
+            _ => panic!("Expected isplit: {}", pos.func.dfg.display_inst(inst, None)),
+        };
+
+        let res = pos.func.dfg.inst_results(inst).to_vec();
+        assert_eq!(res.len(), 2);
+        let (resl, resh) = (res[0], res[1]); // Prevent borrowck error
+
+        let curpos = pos.position();
+        let srcloc = pos.srcloc();
+        let (xl, xh) = split::isplit(pos.func, cfg, curpos, srcloc, arg);
+
+        println!("{}", pos.func);
+        dbg!((xl, xh, resl, resh));
+
+        pos.func.dfg.clear_results(inst);
+        pos.remove_inst();
+        pos.func.dfg.change_to_alias(resl, xl);
+        pos.func.dfg.change_to_alias(resh, xh);
+        println!("{}", pos.func);
+        return true;
     }
 
     match pos.func.update_encoding(inst, isa) {

filetests/isa/x86/i128.clif

@@ -1,12 +1,12 @@
 test compile
 target x86_64
 
-function u0:0(i128) -> i128 fast {
-ebb0(v0: i128):
-    v1 = iconst.i64 0
+function u0:0(i64, i64) -> i128, i64, i64 fast {
+ebb0(v0: i64, v1: i64):
     v2 = iconst.i64 42
-    v3 = iconcat.i64 v2, v1
-    return v3
+    v3 = iconst.i64 0
+    v4 = iconcat.i64 v2, v3
+    return v4, v0, v1
     ; check: v1 = iconst.i64 0
     ; check: v2 = iconst.i64 42
     ; check: return v2, v1, v7