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aarch64: Add specialized
shuffle
lowerings (#5977)
* aarch64: Add `shuffle` lowerings for the `uzp{1,2}` instructions This commit uses the same style of patterns in the x64 backend to start adding specific lowerings of the Cranelift `shuffle` instruction to particular AArch64 instructions. * aarch64: Add `shuffle` lowerings to the `zip{1,2}` instructions These instructions match the `punpck*` family of instructions on x64 and should help provide more efficient lowerings than the current `shuffle` fallback. * aarch64: Add `shuffle` lowerings for `trn{1,2}` Along the lines of prior commits adds specific patterns to lowering for individual AArch64 instructions available. * aarch64: Add a `shuffle` lowering for the `ext` instruction This instruction will more-or-less concatenate two 128-bit vector registers to create a 256-bit value, shift it right, and then take the lower 128-bits into the destination. This can be modeled with a `shuffle` of consecutive bytes so this adds a lowering rule to generate this instruction. * aarch64: Add `shuffle` special case for `dup` This commit adds special cases for Cranelift's `shuffle` on AArch64 when the lowering can be represented with a `dup` instruction which broadcasts one vector's lane into all lanes of the destination. * aarch64: Add `shuffle` specializations for `rev` instructions This commit adds shuffle mask specializations for the `rev{16,32,64}` family of instructions on AArch64 which can be used to reverse bytes, 16-bit values, or 32-bit values within larger values. * Fix tests * Add doc-comments in ISLE
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