Remove the MInst::TrapFf constructor from the riscv64 backend (#5515)

Remove the MInst::TrapFf instruction in the riscv64 backend. It was only used in two places in the emit case for FloatRound, and was easily replaced with a combination of FpuRRR and TrapIf.
bytecodealliance · Jan 4, 2023 · 5d429e4 · 5d429e4
1 parent 4bc4fae
commit 5d429e4
Show file tree

Hide file tree

Showing 3 changed files with 34 additions and 85 deletions.
diff --git a/cranelift/codegen/src/isa/riscv64/inst.isle b/cranelift/codegen/src/isa/riscv64/inst.isle
@@ -108,19 +108,11 @@
       (cc IntCC)
       (trap_code TrapCode))
 
-    (TrapFf
-      (cc FloatCC)
-      (x Reg)
-      (y Reg)
-      (ty Type)
-      (tmp WritableReg)
-      (trap_code TrapCode))
-
     (Jal
       ;; (rd WritableReg) don't use
       (dest BranchTarget))
 
-     (CondBr
+    (CondBr
       (taken BranchTarget)
       (not_taken BranchTarget)
       (kind IntegerCompare))
@@ -2069,15 +2061,6 @@
         (negated Reg (neg $I64 extended)))
     (max $I64 extended negated)))
 
-
-
-(decl gen_trapff (FloatCC Reg Reg Type TrapCode) InstOutput)
-(rule
-  (gen_trapff cc a b ty trap_code)
-  (let
-    ((tmp WritableReg (temp_writable_reg $I64)))
-    (side_effect (SideEffectNoResult.Inst (MInst.TrapFf cc a b ty tmp trap_code)))))
-
 (decl gen_trapif (Reg TrapCode) InstOutput)
 (rule
   (gen_trapif test trap_code)

diff --git a/cranelift/codegen/src/isa/riscv64/inst/emit.rs b/cranelift/codegen/src/isa/riscv64/inst/emit.rs
@@ -1879,15 +1879,28 @@ impl MachInstEmit for Inst {
                     }
                     .iter()
                     .for_each(|i| i.emit(&[], sink, emit_info, state));
-                    Inst::TrapFf {
-                        cc: FloatCC::LessThanOrEqual,
-                        x: rs,
-                        y: tmp.to_reg(),
-                        ty: in_type,
-                        tmp: rd,
+
+                    let le_op = if in_type == F32 {
+                        FpuOPRRR::FleS
+                    } else {
+                        FpuOPRRR::FleD
+                    };
+
+                    // rd := rs <= tmp
+                    Inst::FpuRRR {
+                        alu_op: le_op,
+                        frm: None,
+                        rd,
+                        rs1: rs,
+                        rs2: tmp.to_reg(),
+                    }
+                    .emit(&[], sink, emit_info, state);
+                    Inst::TrapIf {
+                        test: rd.to_reg(),
                         trap_code: TrapCode::IntegerOverflow,
                     }
                     .emit(&[], sink, emit_info, state);
+
                     if in_type == F32 {
                         Inst::load_fp_constant32(tmp, f32_bits(f32_bounds.1), |_| {
                             writable_spilltmp_reg()
@@ -1899,12 +1912,19 @@ impl MachInstEmit for Inst {
                     }
                     .iter()
                     .for_each(|i| i.emit(&[], sink, emit_info, state));
-                    Inst::TrapFf {
-                        cc: FloatCC::GreaterThanOrEqual,
-                        x: rs,
-                        y: tmp.to_reg(),
-                        ty: in_type,
-                        tmp: rd,
+
+                    // rd := rs >= tmp
+                    Inst::FpuRRR {
+                        alu_op: le_op,
+                        frm: None,
+                        rd,
+                        rs1: tmp.to_reg(),
+                        rs2: rs,
+                    }
+                    .emit(&[], sink, emit_info, state);
+
+                    Inst::TrapIf {
+                        test: rd.to_reg(),
                         trap_code: TrapCode::IntegerOverflow,
                     }
                     .emit(&[], sink, emit_info, state);
@@ -2017,39 +2037,6 @@ impl MachInstEmit for Inst {
                 .emit(&[], sink, emit_info, state);
                 sink.bind_label(label_jump_over);
             }
-            &Inst::TrapFf {
-                cc,
-                x,
-                y,
-                ty,
-                trap_code,
-                tmp,
-            } => {
-                let x = allocs.next(x);
-                let y = allocs.next(y);
-                let tmp = allocs.next_writable(tmp);
-                let label_trap = sink.get_label();
-                let label_jump_over = sink.get_label();
-                Inst::lower_br_fcmp(
-                    cc,
-                    x,
-                    y,
-                    BranchTarget::Label(label_trap),
-                    BranchTarget::Label(label_jump_over),
-                    ty,
-                    tmp,
-                )
-                .iter()
-                .for_each(|i| i.emit(&[], sink, emit_info, state));
-                // trap
-                sink.bind_label(label_trap);
-                Inst::Udf {
-                    trap_code: trap_code,
-                }
-                .emit(&[], sink, emit_info, state);
-                sink.bind_label(label_jump_over);
-            }
-
             &Inst::Udf { trap_code } => {
                 sink.add_trap(trap_code);
                 if let Some(s) = state.take_stack_map() {
@@ -2211,6 +2198,7 @@ impl MachInstEmit for Inst {
                 )
                 .into_iter()
                 .for_each(|i| i.emit(&[], sink, emit_info, state));
+
                 //convert to int.
                 Inst::FpuRR {
                     alu_op: FpuOPRR::float_convert_2_int_op(ty, true, I64),

diff --git a/cranelift/codegen/src/isa/riscv64/inst/mod.rs b/cranelift/codegen/src/isa/riscv64/inst/mod.rs
@@ -407,12 +407,6 @@ fn riscv64_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut Operan
         &Inst::TrapIf { test, .. } => {
             collector.reg_use(test);
         }
-        &Inst::TrapFf { x, y, tmp, .. } => {
-            collector.reg_use(x);
-            collector.reg_use(y);
-            collector.reg_early_def(tmp);
-        }
-
         &Inst::Jal { .. } => {}
         &Inst::CondBr { kind, .. } => {
             collector.reg_use(kind.rs1);
@@ -1431,22 +1425,6 @@ impl Inst {
                 let rs2 = format_reg(rs2, allocs);
                 format!("trap_ifc {}##({} {} {})", trap_code, rs1, cc, rs2)
             }
-            &MInst::TrapFf {
-                cc,
-                x,
-                y,
-                ty,
-                trap_code,
-                tmp,
-            } => format!(
-                "trap_ff_{} {} {},{}##tmp={} ty={}",
-                cc,
-                trap_code,
-                format_reg(x, allocs),
-                format_reg(y, allocs),
-                format_reg(tmp.to_reg(), allocs),
-                ty,
-            ),
             &MInst::Jal { dest, .. } => {
                 format!("{} {}", "j", dest)
             }