Support wasm select instruction with V128-typed operands.
#2391
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yurydelendik
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Nov 11, 2020
| @@ -1412,6 +1412,8 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>( | |||
| ctx.emit(Inst::FpuCSel32 { cond, rd, rn, rm }); | |||
| } else if is_float && bits == 64 { | |||
| ctx.emit(Inst::FpuCSel64 { cond, rd, rn, rm }); | |||
| } else if is_float && bits == 128 { | |||
| ctx.emit(Inst::VecCSel { cond, rd, rn, rm }); | |||
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Just to note, it is weird to see that ctx.emit(Inst::CSel ... below did not have assert to prevent float/128 to become csel.
* this requires upgrading to wasmparser 0.67.0. * There are no CLIF side changes because the CLIF `select` instruction is polymorphic enough. * on aarch64, there is unfortunately no conditional-move (csel) instruction on vectors. This patch adds a synthetic instruction `VecCSel` which *does* behave like that. At emit time, this is emitted as an if-then-else diamond (4 insns). * aarch64 implementation is otherwise straightforwards.
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this requires upgrading to wasmparser 0.67.0.
There are no CLIF side changes because the CLIF
selectinstruction ispolymorphic enough.
on aarch64, there is unfortunately no conditional-move (csel) instruction on
vectors. This patch adds a synthetic instruction
VecCSelwhich doesbehave like that. At emit time, this is emitted as an if-then-else diamond
(4 insns).
aarch64 implementation is otherwise straightforwards.