Trap handler changes to support s390x #2871
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On s390x, SIGILL and SIGFPE are delivered with the PSW address pointing *after* the faulting instruction, while SIGSEGV and SIGBUS are delivered with the PSW address pointing *to* the faulting instruction. In order to support this, the common code trap handler has to distinguish between those cases. Also, enable SIGFPE on s390x (just like on x86).
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alexcrichton
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May 3, 2021
| // signals on the first byte of the instruction (as usual). This | ||
| // means we simply need to decrement the reported PSW address by | ||
| // one in the case of a "late" signal here to ensure we always | ||
| // correctly find the associated trap handler. |
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Is there an online link to gist here which goes into some more detail? I'm mostly just curious for my own edification!
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That's a good question. Right now, I don't think this is documented anywhere but by reading the Linux kernel sources. This should probably be added to the ABI document. I've added an issue there as a reminder: IBM/s390x-abi#2
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Ok, sounds reasonable to me!
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On s390x, SIGILL and SIGFPE are delivered with the PSW address pointing *after* the faulting instruction, while SIGSEGV and SIGBUS are delivered with the PSW address pointing *to* the faulting instruction. In order to support this, the common code trap handler has to distinguish between those cases. Also, enable SIGFPE on s390x (just like on x86).
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On s390x, SIGILL and SIGFPE are delivered with the PSW address
pointing after the faulting instruction, while SIGSEGV and
SIGBUS are delivered with the PSW address pointing to the
faulting instruction. In order to support this, the common
code trap handler has to distinguish between those cases.
Also, enable SIGFPE on s390x (just like on x86).