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riscv64: Implement SIMD shifts, v{all,any}_true and vhigh_bits #6507

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merged 5 commits into from
Jun 3, 2023

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@afonso360 afonso360 commented Jun 2, 2023

馃憢 Hey,

This PR implements lowerings for SIMD shifts, and a few boolean operations ( v{all,any}_true/vhigh_bits).

The implementation for shifts is fairly straightforward, but the boolean operations don't have a equivalent instruction, so we need to do some different operations.

@afonso360 afonso360 requested review from a team as code owners June 2, 2023 14:05
@afonso360 afonso360 requested review from elliottt and removed request for a team June 2, 2023 14:05
@github-actions github-actions bot added cranelift Issues related to the Cranelift code generator isle Related to the ISLE domain-specific language labels Jun 2, 2023
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All looks good to me, thanks!

For CI abrupt interruptions like that sometimes mean that QEMU is OOM-ing perhaps because of something like the pooling allocator reserving memory or something like that (or perhaps a flaky run, but we don't get many of those). Other than that though I'm not sure what would cause such a failure in CI.

@elliottt elliottt removed their request for review June 2, 2023 16:42
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This is somewhat weird, I ran it a few times yesterday and it always got canceled. I tested today in my own branch, and it worked, and I just reran CI here and it worked again.

I also tested running the CI tests on my machine and it only used ~500MB, so I'm not entirely sure what is going on. I thought we didn't run any pooling tests on CI due to QEMU issues?

I'm going to tentatively merge this and if it causes issues again, we should revert it and look at it again.

@afonso360 afonso360 added this pull request to the merge queue Jun 3, 2023
Merged via the queue into bytecodealliance:main with commit f7ae056 Jun 3, 2023
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@afonso360 afonso360 deleted the riscv-simd-shifts branch June 3, 2023 16:35
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