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riscv: errata: pgtable: Add custom Svpbmt supported for Allwinner D1
RISC-V Svpbmt is gradually maturing, the draft is: Svpbmt PTE format: | 63 | 62-61 | 60-8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 N MT RSW D A G U X W R V ^ Of the Reserved bits [63:54] in a leaf PTE, the high bit is already allocated (as the N bit), so bits [62:61] are used as the MT (aka MemType) field. This field specifies one of three memory types that are close equivalents (or equivalent in effect) to the three main x86 and ARMv8 memory types - as shown in the following table. RISC-V Encoding & MemType RISC-V Description ---------- ------------------------------------------------ 00 - PMA Normal Cacheable, No change to implied PMA memory type 01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory 11 - Rsvd Reserved for future standard use But T-HEAD C906 in Allwinner D1 has defined a custom Svpbmt: T-HEAD C9xx PTE format: | 63 | 62 | 61 | 60 | 59-8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 SO C B SH RSW D A G U X W R V ^ ^ ^ ^ BIT(63): SO - Strong Order BIT(62): C - Cacheable BIT(61): B - Bufferable BIT(60): SH - Shareable MT_MASK : [63 - 59] MT_PMA : C + SH MT_NC : (none) MT_IO : SO The patch not only implements the D1's PBMT extension but also considers future scalability by errata framework. We are trying to keep both below work together: - "riscv spec acceptance policy" (Svpbmt extension in future) - "Linux Keep real hardware work" (Allwinner D1's custom Svpbmt) Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Liu Shaohua <liush@allwinnertech.com> Signed-off-by: Wei Fu <wefu@redhat.com> Cc: Palmer Dabbelt <palmerdabbelt@google.com> Cc: Christoph Hellwig <hch@lst.de> Cc: Anup Patel <anup.patel@wdc.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Drew Fustini <drew@beagleboard.org> Cc: Wei Fu <wefu@redhat.com> Cc: Wei Wu <lazyparser@gmail.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Maxime Ripard <maxime@cerno.tech> Cc: Daniel Lustig <dlustig@nvidia.com> Cc: Greg Favor <gfavor@ventanamicro.com> Cc: Andrea Mondelli <andrea.mondelli@huawei.com> Cc: Jonathan Behrens <behrensj@mit.edu> Cc: Xinhaoqu (Freddie) <xinhaoqu@huawei.com> Cc: Bill Huffman <huffman@cadence.com> Cc: Nick Kossifidis <mick@ics.forth.gr> Cc: Allen Baum <allen.baum@esperantotech.com> Cc: Josh Scheid <jscheid@ventanamicro.com> Cc: Richard Trauben <rtrauben@gmail.com>
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obj-y += alternative.o | ||
obj-$(CONFIG_ERRATA_SIFIVE) += sifive/ | ||
obj-$(CONFIG_ERRATA_THEAD) += thead/ |
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obj-y += errata.o |
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// SPDX-License-Identifier: GPL-2.0-only | ||
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#include <linux/kernel.h> | ||
#include <linux/string.h> | ||
#include <linux/bug.h> | ||
#include <linux/mm.h> | ||
#include <asm/patch.h> | ||
#include <asm/alternative.h> | ||
#include <asm/vendorid_list.h> | ||
#include <asm/errata_list.h> | ||
#include <asm/pgtable.h> | ||
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/* | ||
* T-HEAD C9xx PTE format: | ||
* | 63 | 62 | 61 | 60 | 59-8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||
* SO C B SH RSW D A G U X W R V | ||
* ^ ^ ^ ^ ^ | ||
* BIT(63): SO - Strong Order | ||
* BIT(62): C - Cacheable | ||
* BIT(61): B - Bufferable | ||
* BIT(60): SH - Shareable | ||
* | ||
* MT_MASK : [63 - 59] | ||
* MT_PMA : C + SH | ||
* MT_NC : (none) | ||
* MT_IO : SO | ||
*/ | ||
void __init thead_errata_setup_vm(unsigned long archid, unsigned long impid) | ||
{ | ||
int i; | ||
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#ifdef CONFIG_64BIT | ||
__riscv_svpbmt.mask = 0xf800000000000000; | ||
__riscv_svpbmt.mt_pma = 0x5000000000000000; | ||
__riscv_svpbmt.mt_nc = 0x0; | ||
__riscv_svpbmt.mt_io = 0x8000000000000000; | ||
#endif | ||
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for (i = 0; i < 16; i++) | ||
pgprot_val(protection_map[i]) |= __riscv_svpbmt.mt_pma; | ||
} |
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#define ASM_VENDOR_LIST_H | ||
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#define SIFIVE_VENDOR_ID 0x489 | ||
#define THEAD_VENDOR_ID 0x5b7 | ||
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#endif |
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