Skip to content

Commit

Permalink
Put early-transitions behind a flag
Browse files Browse the repository at this point in the history
  • Loading branch information
@rachitnigam
rachitnigam committed Nov 19, 2021
1 parent 99d9d87 commit 0823c99
Show file tree
Hide file tree
Showing 26 changed files with 88 additions and 114 deletions.
16 changes: 8 additions & 8 deletions calyx/src/passes/top_down_compile_control.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -592,8 +592,8 @@ fn calculate_states(
pub struct TopDownCompileControl {
/// Print out the FSM representation to STDOUT
dump_fsm: bool,
/// Disable early transitions
no_early_transitions: bool,
/// Enable early transitions
early_transitions: bool,
}

impl ConstructVisitor for TopDownCompileControl {
Expand All @@ -602,24 +602,24 @@ impl ConstructVisitor for TopDownCompileControl {
Self: Sized + Named,
{
let mut dump_fsm = false;
let mut no_early_transitions = false;
let mut early_transitions = false;
ctx.extra_opts.iter().for_each(|opt| {
let mut splits = opt.split(':');
if splits.next() == Some(Self::name()) {
match splits.next() {
Some("dump-fsm") => {
dump_fsm = true;
}
Some("no-early-transitions") => {
no_early_transitions = true;
Some("early-transitions") => {
early_transitions = true;
}
_ => (),
}
}
});
Ok(TopDownCompileControl {
dump_fsm,
no_early_transitions,
early_transitions,
})
}

Expand Down Expand Up @@ -690,7 +690,7 @@ impl Visitor for TopDownCompileControl {
let schedule = calculate_states(
con,
&mut builder,
!self.no_early_transitions,
self.early_transitions,
)?;
let group = builder.add_group("tdcc");
if self.dump_fsm {
Expand Down Expand Up @@ -771,7 +771,7 @@ impl Visitor for TopDownCompileControl {
let schedule = calculate_states(
&control.borrow(),
&mut builder,
!self.no_early_transitions,
self.early_transitions,
)?;
let group = builder.add_group("tdcc");
if self.dump_fsm {
Expand Down
2 changes: 1 addition & 1 deletion examples/dahlia/dot-product.expect
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
{
"cycles": 92,
"cycles": 125,
"memories": {
"A0": [
27,
Expand Down
2 changes: 1 addition & 1 deletion examples/dahlia/vectorized-add.expect
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
{
"cycles": 44,
"cycles": 77,
"memories": {
"A0": [
1,
Expand Down
58 changes: 29 additions & 29 deletions examples/futil/dot-product.expect
View file
Original file line number Diff line number Diff line change
Expand Up @@ -23,32 +23,32 @@ component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
@generated fsm = std_reg(4);
}
wires {
A0.addr0 = !(pd.out | A_read0_0.done) & (comb_reg.done & comb_reg.out & fsm.out == 4'd1 & go | !(pd.out & pd0.out) & fsm.out == 4'd2 & go | comb_reg.done & comb_reg.out & fsm.out == 4'd7 & go) ? i0.out;
A0.addr0 = !(pd.out | A_read0_0.done) & !(pd.out & pd0.out) & fsm.out == 4'd2 & go ? i0.out;
A0.clk = clk;
A_read0_0.clk = clk;
A_read0_0.in = !(pd.out | A_read0_0.done) & (comb_reg.done & comb_reg.out & fsm.out == 4'd1 & go | !(pd.out & pd0.out) & fsm.out == 4'd2 & go | comb_reg.done & comb_reg.out & fsm.out == 4'd7 & go) ? A0.read_data;
A_read0_0.in = bin_read0_0.done & fsm.out == 4'd3 & go | !A_read0_0.done & fsm.out == 4'd4 & go ? bin_read0_0.out;
A_read0_0.in = !(pd.out | A_read0_0.done) & !(pd.out & pd0.out) & fsm.out == 4'd2 & go ? A0.read_data;
A_read0_0.in = !A_read0_0.done & fsm.out == 4'd4 & go ? bin_read0_0.out;
A_read0_0.reset = reset;
A_read0_0.write_en = bin_read0_0.done & fsm.out == 4'd3 & go | !A_read0_0.done & fsm.out == 4'd4 & go | !(pd.out | A_read0_0.done) & (comb_reg.done & comb_reg.out & fsm.out == 4'd1 & go | !(pd.out & pd0.out) & fsm.out == 4'd2 & go | comb_reg.done & comb_reg.out & fsm.out == 4'd7 & go) ? 1'd1;
B0.addr0 = !(pd0.out | B_read0_0.done) & (comb_reg.done & comb_reg.out & fsm.out == 4'd1 & go | !(pd.out & pd0.out) & fsm.out == 4'd2 & go | comb_reg.done & comb_reg.out & fsm.out == 4'd7 & go) ? i0.out;
A_read0_0.write_en = !A_read0_0.done & fsm.out == 4'd4 & go | !(pd.out | A_read0_0.done) & !(pd.out & pd0.out) & fsm.out == 4'd2 & go ? 1'd1;
B0.addr0 = !(pd0.out | B_read0_0.done) & !(pd.out & pd0.out) & fsm.out == 4'd2 & go ? i0.out;
B0.clk = clk;
B_read0_0.clk = clk;
B_read0_0.in = !(pd0.out | B_read0_0.done) & (comb_reg.done & comb_reg.out & fsm.out == 4'd1 & go | !(pd.out & pd0.out) & fsm.out == 4'd2 & go | comb_reg.done & comb_reg.out & fsm.out == 4'd7 & go) ? B0.read_data;
B_read0_0.in = !(pd0.out | B_read0_0.done) & !(pd.out & pd0.out) & fsm.out == 4'd2 & go ? B0.read_data;
B_read0_0.reset = reset;
B_read0_0.write_en = !(pd0.out | B_read0_0.done) & (comb_reg.done & comb_reg.out & fsm.out == 4'd1 & go | !(pd.out & pd0.out) & fsm.out == 4'd2 & go | comb_reg.done & comb_reg.out & fsm.out == 4'd7 & go) ? 1'd1;
B_read0_0.write_en = !(pd0.out | B_read0_0.done) & !(pd.out & pd0.out) & fsm.out == 4'd2 & go ? 1'd1;
done = fsm.out == 4'd8 ? 1'd1;
add0.left = A_read0_0.done & fsm.out == 4'd4 & go | !v0.done & fsm.out == 4'd5 & go ? v0.read_data;
add0.right = A_read0_0.done & fsm.out == 4'd4 & go | !v0.done & fsm.out == 4'd5 & go ? A_read0_0.out;
add1.left = v0.done & fsm.out == 4'd5 & go | !i0.done & fsm.out == 4'd6 & go ? i0.out;
add1.right = v0.done & fsm.out == 4'd5 & go | !i0.done & fsm.out == 4'd6 & go ? const3.out;
add0.left = !v0.done & fsm.out == 4'd5 & go ? v0.read_data;
add0.right = !v0.done & fsm.out == 4'd5 & go ? A_read0_0.out;
add1.left = !i0.done & fsm.out == 4'd6 & go ? i0.out;
add1.right = !i0.done & fsm.out == 4'd6 & go ? const3.out;
bin_read0_0.clk = clk;
bin_read0_0.in = pd.out & pd0.out & fsm.out == 4'd2 & go | !bin_read0_0.done & fsm.out == 4'd3 & go ? mult_pipe0.out;
bin_read0_0.in = !bin_read0_0.done & fsm.out == 4'd3 & go ? mult_pipe0.out;
bin_read0_0.reset = reset;
bin_read0_0.write_en = pd.out & pd0.out & fsm.out == 4'd2 & go | !bin_read0_0.done & fsm.out == 4'd3 & go ? mult_pipe0.done;
bin_read0_0.write_en = !bin_read0_0.done & fsm.out == 4'd3 & go ? mult_pipe0.done;
comb_reg.clk = clk;
comb_reg.in = i0.done & fsm.out == 4'd0 & go | !comb_reg.done & fsm.out == 4'd1 & go | i0.done & fsm.out == 4'd6 & go | !comb_reg.done & fsm.out == 4'd7 & go ? le0.out;
comb_reg.in = !comb_reg.done & fsm.out == 4'd1 & go | !comb_reg.done & fsm.out == 4'd7 & go ? le0.out;
comb_reg.reset = reset;
comb_reg.write_en = i0.done & fsm.out == 4'd0 & go | !comb_reg.done & fsm.out == 4'd1 & go | i0.done & fsm.out == 4'd6 & go | !comb_reg.done & fsm.out == 4'd7 & go ? 1'd1;
comb_reg.write_en = !comb_reg.done & fsm.out == 4'd1 & go | !comb_reg.done & fsm.out == 4'd7 & go ? 1'd1;
fsm.clk = clk;
fsm.in = fsm.out == 4'd8 ? 4'd0;
fsm.in = fsm.out == 4'd0 & i0.done & go ? 4'd1;
Expand All @@ -62,31 +62,31 @@ component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
fsm.reset = reset;
fsm.write_en = fsm.out == 4'd0 & i0.done & go | fsm.out == 4'd1 & comb_reg.done & comb_reg.out & go | fsm.out == 4'd7 & comb_reg.done & comb_reg.out & go | fsm.out == 4'd2 & pd.out & pd0.out & go | fsm.out == 4'd3 & bin_read0_0.done & go | fsm.out == 4'd4 & A_read0_0.done & go | fsm.out == 4'd5 & v0.done & go | fsm.out == 4'd6 & i0.done & go | fsm.out == 4'd1 & comb_reg.done & !comb_reg.out & go | fsm.out == 4'd7 & comb_reg.done & !comb_reg.out & go | fsm.out == 4'd8 ? 1'd1;
i0.clk = clk;
i0.in = v0.done & fsm.out == 4'd5 & go | !i0.done & fsm.out == 4'd6 & go ? add1.out;
i0.in = !i0.done & fsm.out == 4'd6 & go ? add1.out;
i0.in = !i0.done & fsm.out == 4'd0 & go ? const0.out;
i0.reset = reset;
i0.write_en = !i0.done & fsm.out == 4'd0 & go | v0.done & fsm.out == 4'd5 & go | !i0.done & fsm.out == 4'd6 & go ? 1'd1;
le0.left = i0.done & fsm.out == 4'd0 & go | !comb_reg.done & fsm.out == 4'd1 & go | i0.done & fsm.out == 4'd6 & go | !comb_reg.done & fsm.out == 4'd7 & go ? i0.out;
le0.right = i0.done & fsm.out == 4'd0 & go | !comb_reg.done & fsm.out == 4'd1 & go | i0.done & fsm.out == 4'd6 & go | !comb_reg.done & fsm.out == 4'd7 & go ? const1.out;
i0.write_en = !i0.done & fsm.out == 4'd0 & go | !i0.done & fsm.out == 4'd6 & go ? 1'd1;
le0.left = !comb_reg.done & fsm.out == 4'd1 & go | !comb_reg.done & fsm.out == 4'd7 & go ? i0.out;
le0.right = !comb_reg.done & fsm.out == 4'd1 & go | !comb_reg.done & fsm.out == 4'd7 & go ? const1.out;
mult_pipe0.clk = clk;
mult_pipe0.go = !mult_pipe0.done & (pd.out & pd0.out & fsm.out == 4'd2 & go | !bin_read0_0.done & fsm.out == 4'd3 & go) ? 1'd1;
mult_pipe0.left = pd.out & pd0.out & fsm.out == 4'd2 & go | !bin_read0_0.done & fsm.out == 4'd3 & go ? A_read0_0.out;
mult_pipe0.go = !mult_pipe0.done & !bin_read0_0.done & fsm.out == 4'd3 & go ? 1'd1;
mult_pipe0.left = !bin_read0_0.done & fsm.out == 4'd3 & go ? A_read0_0.out;
mult_pipe0.reset = reset;
mult_pipe0.right = pd.out & pd0.out & fsm.out == 4'd2 & go | !bin_read0_0.done & fsm.out == 4'd3 & go ? B_read0_0.out;
mult_pipe0.right = !bin_read0_0.done & fsm.out == 4'd3 & go ? B_read0_0.out;
pd.clk = clk;
pd.in = pd.out & pd0.out ? 1'd0;
pd.in = A_read0_0.done & (comb_reg.done & comb_reg.out & fsm.out == 4'd1 & go | !(pd.out & pd0.out) & fsm.out == 4'd2 & go | comb_reg.done & comb_reg.out & fsm.out == 4'd7 & go) ? 1'd1;
pd.in = A_read0_0.done & !(pd.out & pd0.out) & fsm.out == 4'd2 & go ? 1'd1;
pd.reset = reset;
pd.write_en = A_read0_0.done & (comb_reg.done & comb_reg.out & fsm.out == 4'd1 & go | !(pd.out & pd0.out) & fsm.out == 4'd2 & go | comb_reg.done & comb_reg.out & fsm.out == 4'd7 & go) | pd.out & pd0.out ? 1'd1;
pd.write_en = A_read0_0.done & !(pd.out & pd0.out) & fsm.out == 4'd2 & go | pd.out & pd0.out ? 1'd1;
pd0.clk = clk;
pd0.in = pd.out & pd0.out ? 1'd0;
pd0.in = B_read0_0.done & (comb_reg.done & comb_reg.out & fsm.out == 4'd1 & go | !(pd.out & pd0.out) & fsm.out == 4'd2 & go | comb_reg.done & comb_reg.out & fsm.out == 4'd7 & go) ? 1'd1;
pd0.in = B_read0_0.done & !(pd.out & pd0.out) & fsm.out == 4'd2 & go ? 1'd1;
pd0.reset = reset;
pd0.write_en = B_read0_0.done & (comb_reg.done & comb_reg.out & fsm.out == 4'd1 & go | !(pd.out & pd0.out) & fsm.out == 4'd2 & go | comb_reg.done & comb_reg.out & fsm.out == 4'd7 & go) | pd.out & pd0.out ? 1'd1;
v0.addr0 = A_read0_0.done & fsm.out == 4'd4 & go | !v0.done & fsm.out == 4'd5 & go ? const2.out;
pd0.write_en = B_read0_0.done & !(pd.out & pd0.out) & fsm.out == 4'd2 & go | pd.out & pd0.out ? 1'd1;
v0.addr0 = !v0.done & fsm.out == 4'd5 & go ? const2.out;
v0.clk = clk;
v0.write_data = A_read0_0.done & fsm.out == 4'd4 & go | !v0.done & fsm.out == 4'd5 & go ? add0.out;
v0.write_en = A_read0_0.done & fsm.out == 4'd4 & go | !v0.done & fsm.out == 4'd5 & go ? 1'd1;
v0.write_data = !v0.done & fsm.out == 4'd5 & go ? add0.out;
v0.write_en = !v0.done & fsm.out == 4'd5 & go ? 1'd1;
}

control {}
Expand Down
4 changes: 2 additions & 2 deletions examples/futil/multi-component.expect
View file
Original file line number Diff line number Diff line change
Expand Up @@ -23,9 +23,9 @@ component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
wires {
done = fsm.out == 2'd2 ? 1'd1;
current_value.clk = clk;
current_value.in = id.done & fsm.out == 2'd0 & go | !current_value.done & fsm.out == 2'd1 & go ? id.out;
current_value.in = !current_value.done & fsm.out == 2'd1 & go ? id.out;
current_value.reset = reset;
current_value.write_en = id.done & fsm.out == 2'd0 & go | !current_value.done & fsm.out == 2'd1 & go ? 1'd1;
current_value.write_en = !current_value.done & fsm.out == 2'd1 & go ? 1'd1;
fsm.clk = clk;
fsm.in = fsm.out == 2'd2 ? 2'd0;
fsm.in = fsm.out == 2'd0 & id.done & go ? 2'd1;
Expand Down
10 changes: 5 additions & 5 deletions examples/futil/pass-in-register.expect
View file
Original file line number Diff line number Diff line change
Expand Up @@ -32,16 +32,16 @@ component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
fsm.reset = reset;
fsm.write_en = fsm.out == 2'd0 & r.done & go | fsm.out == 2'd1 & op.done & go | fsm.out == 2'd2 ? 1'd1;
op.clk = clk;
op.go = r.done & fsm.out == 2'd0 & go | !op.done & fsm.out == 2'd1 & go ? 1'd1;
op.reg_done = r.done & fsm.out == 2'd0 & go | !op.done & fsm.out == 2'd1 & go ? r.done;
op.reg_out = r.done & fsm.out == 2'd0 & go | !op.done & fsm.out == 2'd1 & go ? r.out;
op.go = !op.done & fsm.out == 2'd1 & go ? 1'd1;
op.reg_done = !op.done & fsm.out == 2'd1 & go ? r.done;
op.reg_out = !op.done & fsm.out == 2'd1 & go ? r.out;
op.reset = reset;
r.clk = clk;
r.in = !r.done & fsm.out == 2'd0 & go ? 32'd15;
r.in = r.done & fsm.out == 2'd0 & go | !op.done & fsm.out == 2'd1 & go ? op.reg_in;
r.in = !op.done & fsm.out == 2'd1 & go ? op.reg_in;
r.reset = reset;
r.write_en = !r.done & fsm.out == 2'd0 & go ? 1'd1;
r.write_en = r.done & fsm.out == 2'd0 & go | !op.done & fsm.out == 2'd1 & go ? op.reg_write_en;
r.write_en = !op.done & fsm.out == 2'd1 & go ? op.reg_write_en;
}

control {}
Expand Down
10 changes: 5 additions & 5 deletions examples/futil/simple.expect
View file
Original file line number Diff line number Diff line change
Expand Up @@ -21,18 +21,18 @@ component main(@go go: 1, @clk clk: 1, @reset reset: 1) -> (@done done: 1) {
fsm.reset = reset;
fsm.write_en = fsm.out == 2'd0 & reg0.done & go | fsm.out == 2'd1 & reg1.done & go | fsm.out == 2'd2 ? 1'd1;
mult.clk = clk;
mult.go = !mult.done & (reg0.done & fsm.out == 2'd0 & go | !reg1.done & fsm.out == 2'd1 & go) ? 1'd1;
mult.left = reg0.done & fsm.out == 2'd0 & go | !reg1.done & fsm.out == 2'd1 & go ? const0.out;
mult.go = !mult.done & !reg1.done & fsm.out == 2'd1 & go ? 1'd1;
mult.left = !reg1.done & fsm.out == 2'd1 & go ? const0.out;
mult.reset = reset;
mult.right = reg0.done & fsm.out == 2'd0 & go | !reg1.done & fsm.out == 2'd1 & go ? const1.out;
mult.right = !reg1.done & fsm.out == 2'd1 & go ? const1.out;
reg0.clk = clk;
reg0.in = !reg0.done & fsm.out == 2'd0 & go ? add.out;
reg0.reset = reset;
reg0.write_en = !reg0.done & fsm.out == 2'd0 & go ? 1'd1;
reg1.clk = clk;
reg1.in = reg0.done & fsm.out == 2'd0 & go | !reg1.done & fsm.out == 2'd1 & go ? mult.out;
reg1.in = !reg1.done & fsm.out == 2'd1 & go ? mult.out;
reg1.reset = reset;
reg1.write_en = reg0.done & fsm.out == 2'd0 & go | !reg1.done & fsm.out == 2'd1 & go ? mult.done;
reg1.write_en = !reg1.done & fsm.out == 2'd1 & go ? mult.done;
}

control {}
Expand Down
Loading

0 comments on commit 0823c99

Please sign in to comment.