Remove repetitive words (#2297)

capstone-engine · Mar 23, 2024 · 0d12bca · 0d12bca
1 parent 5d9942d
commit 0d12bca
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Showing 5 changed files with 5 additions and 5 deletions.
diff --git a/COMPILE_CMAKE.TXT b/COMPILE_CMAKE.TXT
@@ -45,7 +45,7 @@ Get CMake for free from http://www.cmake.org.
   By default, all architectures are compiled in. If you're building a static library that you intend to link into
   multiple consumers, and they have differing architecture requirements, you may want -DCAPSTONE_USE_ARCH_REGISTRATION=1
   and call cs_arch_register_*() for the architectures you need in each particular consumer. In this way you only pay
-  footprint size for the the architectures you're actually using in each consumer, without having to compile Capstone
+  footprint size for the architectures you're actually using in each consumer, without having to compile Capstone
   multiple times.
 
   Besides, Capstone also allows some more customization via following macros.

diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/CodeGenPassBuilder.h b/suite/synctools/tablegen/include/llvm/CodeGen/CodeGenPassBuilder.h
@@ -295,7 +295,7 @@ template <typename DerivedT> class CodeGenPassBuilder {
   /// all virtual registers.
   ///
   /// Note if the target overloads addRegAssignAndRewriteOptimized, this may not
-  /// be honored. This is also not generally used for the the fast variant,
+  /// be honored. This is also not generally used for the fast variant,
   /// where the allocation and rewriting are done in one pass.
   void addPreRewrite(AddMachinePass &) const {}
 

diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
@@ -238,7 +238,7 @@ class LegalizerHelper {
   /// needs to be widened to evenly cover \p DstReg, inserts high bits
   /// corresponding to the extension opcode \p PadStrategy.
   ///
-  /// \p VRegs will be cleared, and the the result \p NarrowTy register pieces
+  /// \p VRegs will be cleared, and the result \p NarrowTy register pieces
   /// will replace it. Returns The complete LCMTy that \p VRegs will cover when
   /// merged.
   LLT buildLCMMergePieces(LLT DstTy, LLT NarrowTy, LLT GCDTy,

diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/LiveInterval.h b/suite/synctools/tablegen/include/llvm/CodeGen/LiveInterval.h
@@ -851,7 +851,7 @@ namespace llvm {
     /// V2: sub0 sub1 sub2 sub3
     /// V1: <offset>  sub0 sub1
     ///
-    /// This offset will look like a composed subregidx in the the class:
+    /// This offset will look like a composed subregidx in the class:
     ///     V1.(composed sub2 with sub1):<4 x s32> = COPY V2.sub3:<4 x s32>
     /// =>  V1.(composed sub2 with sub1):<4 x s32> = COPY V2.sub3:<4 x s32>
     ///

diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/TargetPassConfig.h b/suite/synctools/tablegen/include/llvm/CodeGen/TargetPassConfig.h
@@ -398,7 +398,7 @@ class TargetPassConfig : public ImmutablePass {
   /// all virtual registers.
   ///
   /// Note if the target overloads addRegAssignAndRewriteOptimized, this may not
-  /// be honored. This is also not generally used for the the fast variant,
+  /// be honored. This is also not generally used for the fast variant,
   /// where the allocation and rewriting are done in one pass.
   virtual bool addPreRewrite() {
     return false;