Add SYS ops test to cstest

capstone-engine · Mar 22, 2022 · 1d9ea9c · 1d9ea9c
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Showing 2 changed files with 20 additions and 37 deletions.
diff --git a/suite/cstest/issues.cs b/suite/cstest/issues.cs
@@ -1,3 +1,23 @@
+!# issue 1856 AArch64 SYS instruction operands: tlbi 1 op
+!# CS_ARCH_ARM64, CS_MODE_ARM, CS_OPT_DETAIL
+0x1f,0x83,0x08,0xd5 == tlbi vmalle1is ; op_count: 1 ; operands[0].type: SYS = 0x3
+
+!# issue 1856 AArch64 SYS instruction operands: tlbi 2 op
+!# CS_ARCH_ARM64, CS_MODE_ARM, CS_OPT_DETAIL
+0x22,0x87,0x08,0xd5 == tlbi vae1, x2 ; op_count: 2 ; operands[0].type: SYS = 0x16
+
+!# issue 1856 AArch64 SYS instruction operands: at
+!# CS_ARCH_ARM64, CS_MODE_ARM, CS_OPT_DETAIL
+0xc0,0x78,0x0c,0xd5 == at s12e0r, x0 ; op_count: 2 ; operands[0].type: SYS = 0x59
+
+!# issue 1856 AArch64 SYS instruction operands: dc
+!# CS_ARCH_ARM64, CS_MODE_ARM, CS_OPT_DETAIL
+0x22,0x7b,0x0b,0xd5 == dc cvau, x2 ; op_count: 2 ; operands[0].type: SYS = 0x62
+
+!# issue 1856 AArch64 SYS instruction operands: ic
+!# CS_ARCH_ARM64, CS_MODE_ARM, CS_OPT_DETAIL
+0x20,0x75,0x0b,0xd5 == ic ivau, x0 ; op_count: 2 ; operands[0].type: SYS = 0x68
+
 !# issue 1839 AArch64 Incorrect detailed disassembly of ldr
 !# CS_ARCH_ARM64, CS_MODE_ARM, CS_OPT_DETAIL
 0x41,0x00,0x40,0xf9 == ldr x1, [x2] ; operands[0].access: WRITE ; operands[1].access: READ

diff --git a/suite/regress/test_arm64_sys_op.py b/suite/regress/test_arm64_sys_op.py