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ARM/AArch64: Add post-index to instruction info #1937

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merged 5 commits into from
Nov 24, 2022
Merged

ARM/AArch64: Add post-index to instruction info #1937

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1e416c8
Add post_index field for cs_arm64
ZehMatt Nov 22, 2022
f6bfc9f
Add instructions with pre and post index to test_arm64
ZehMatt Nov 22, 2022
6d6debe
Add post_index to arm
ZehMatt Nov 22, 2022
7939e88
Update comment
ZehMatt Nov 22, 2022
784aa0f
Add post_index to python bindings
ZehMatt Nov 22, 2022
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111 changes: 57 additions & 54 deletions arch/AArch64/AArch64InstPrinter.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2864,48 +2864,18 @@ void AArch64_post_printer(csh handle, cs_insn *flat_insn, char *insn_asm, MCInst
case AArch64_LD4i32_POST:
case AArch64_LD4i64_POST:
case AArch64_LD4i8_POST:
case AArch64_LDPDpost:
case AArch64_LDPDpre:
case AArch64_LDPQpost:
case AArch64_LDPQpre:
case AArch64_LDPSWpost:
case AArch64_LDPSWpre:
case AArch64_LDPSpost:
case AArch64_LDPSpre:
case AArch64_LDPWpost:
case AArch64_LDPWpre:
case AArch64_LDPXpost:
case AArch64_LDPXpre:
case AArch64_LDRAAwriteback:
case AArch64_LDRABwriteback:
case AArch64_LDRBBpost:
case AArch64_LDRBBpre:
case AArch64_LDRBpost:
case AArch64_LDRBpre:
case AArch64_LDRDpost:
case AArch64_LDRDpre:
case AArch64_LDRHHpost:
case AArch64_LDRHHpre:
case AArch64_LDRHpost:
case AArch64_LDRHpre:
case AArch64_LDRQpost:
case AArch64_LDRQpre:
case AArch64_LDRSBWpost:
case AArch64_LDRSBWpre:
case AArch64_LDRSBXpost:
case AArch64_LDRSBXpre:
case AArch64_LDRSHWpost:
case AArch64_LDRSHWpre:
case AArch64_LDRSHXpost:
case AArch64_LDRSHXpre:
case AArch64_LDRSWpost:
case AArch64_LDRSWpre:
case AArch64_LDRSpost:
case AArch64_LDRSpre:
case AArch64_LDRWpost:
case AArch64_LDRWpre:
case AArch64_LDRXpost:
case AArch64_LDRXpre:
case AArch64_LDPDpost:
case AArch64_LDPQpost:
case AArch64_LDPSWpost:
case AArch64_LDPSpost:
case AArch64_LDPWpost:
case AArch64_LDPXpost:
case AArch64_ST1Fourv16b_POST:
case AArch64_ST1Fourv1d_POST:
case AArch64_ST1Fourv2d_POST:
Expand Down Expand Up @@ -2943,7 +2913,6 @@ void AArch64_post_printer(csh handle, cs_insn *flat_insn, char *insn_asm, MCInst
case AArch64_ST1i64_POST:
case AArch64_ST1i8_POST:
case AArch64_ST2GPostIndex:
case AArch64_ST2GPreIndex:
case AArch64_ST2Twov16b_POST:
case AArch64_ST2Twov2d_POST:
case AArch64_ST2Twov2s_POST:
Expand Down Expand Up @@ -2977,42 +2946,76 @@ void AArch64_post_printer(csh handle, cs_insn *flat_insn, char *insn_asm, MCInst
case AArch64_ST4i32_POST:
case AArch64_ST4i64_POST:
case AArch64_ST4i8_POST:
case AArch64_STPDpost:
case AArch64_STPQpost:
case AArch64_STPSpost:
case AArch64_STPWpost:
case AArch64_STPXpost:
case AArch64_STRBBpost:
case AArch64_STRBpost:
case AArch64_STRDpost:
case AArch64_STRHHpost:
case AArch64_STRHpost:
case AArch64_STRQpost:
case AArch64_STRSpost:
case AArch64_STRWpost:
case AArch64_STRXpost:
case AArch64_STZ2GPostIndex:
case AArch64_STZGPostIndex:
case AArch64_STGPostIndex:
case AArch64_STGPpost:
case AArch64_STGPpre:
case AArch64_LDRSBWpost:
case AArch64_LDRSBXpost:
case AArch64_LDRSHWpost:
case AArch64_LDRSHXpost:
case AArch64_LDRSWpost:
case AArch64_LDRSpost:
case AArch64_LDRWpost:
case AArch64_LDRXpost:
flat_insn->detail->arm64.writeback = true;
flat_insn->detail->arm64.post_index = true;
break;
case AArch64_LDRAAwriteback:
case AArch64_LDRABwriteback:
case AArch64_ST2GPreIndex:
case AArch64_LDPDpre:
case AArch64_LDPQpre:
case AArch64_LDPSWpre:
case AArch64_LDPSpre:
case AArch64_LDPWpre:
case AArch64_LDPXpre:
case AArch64_LDRBBpre:
case AArch64_LDRBpre:
case AArch64_LDRDpre:
case AArch64_LDRHHpre:
case AArch64_LDRHpre:
case AArch64_LDRQpre:
case AArch64_LDRSBWpre:
case AArch64_LDRSBXpre:
case AArch64_LDRSHWpre:
case AArch64_LDRSHXpre:
case AArch64_LDRSWpre:
case AArch64_LDRSpre:
case AArch64_LDRWpre:
case AArch64_LDRXpre:
case AArch64_STGPreIndex:
case AArch64_STPDpost:
case AArch64_STPDpre:
case AArch64_STPQpost:
case AArch64_STPQpre:
case AArch64_STPSpost:
case AArch64_STPSpre:
case AArch64_STPWpost:
case AArch64_STPWpre:
case AArch64_STPXpost:
case AArch64_STPXpre:
case AArch64_STRBBpost:
case AArch64_STRBBpre:
case AArch64_STRBpost:
case AArch64_STRBpre:
case AArch64_STRDpost:
case AArch64_STRDpre:
case AArch64_STRHHpost:
case AArch64_STRHHpre:
case AArch64_STRHpost:
case AArch64_STRHpre:
case AArch64_STRQpost:
case AArch64_STRQpre:
case AArch64_STRSpost:
case AArch64_STRSpre:
case AArch64_STRWpost:
case AArch64_STRWpre:
case AArch64_STRXpost:
case AArch64_STRXpre:
case AArch64_STZ2GPostIndex:
case AArch64_STZ2GPreIndex:
case AArch64_STZGPostIndex:
case AArch64_STZGPreIndex:
case AArch64_STGPpre:
flat_insn->detail->arm64.writeback = true;
break;
}
Expand Down
9 changes: 6 additions & 3 deletions arch/ARM/ARMInstPrinter.c
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Original file line number Diff line number Diff line change
Expand Up @@ -318,7 +318,8 @@ void ARM_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
case ARM_t2STRD_PRE:
case ARM_t2STRH_PRE:
case ARM_t2STR_PRE:

insn->detail->arm.writeback = true;
break;
case ARM_t2LDC2L_POST:
case ARM_t2LDC2_POST:
case ARM_t2LDCL_POST:
Expand All @@ -341,6 +342,7 @@ void ARM_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
case ARM_t2STRH_POST:
case ARM_t2STR_POST:
insn->detail->arm.writeback = true;
insn->detail->arm.post_index = true;
break;
}
} else { // ARM mode
Expand All @@ -366,7 +368,8 @@ void ARM_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)

case ARM_STRD_PRE:
case ARM_STRH_PRE:

insn->detail->arm.writeback = true;
break;
case ARM_LDC2L_POST:
case ARM_LDC2_POST:
case ARM_LDCL_POST:
Expand Down Expand Up @@ -394,8 +397,8 @@ void ARM_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)

case ARM_STR_POST_IMM:
case ARM_STR_POST_REG:

insn->detail->arm.writeback = true;
insn->detail->arm.post_index = true;
break;
}
}
Expand Down
3 changes: 2 additions & 1 deletion bindings/python/capstone/arm.py
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Original file line number Diff line number Diff line change
Expand Up @@ -71,12 +71,13 @@ class CsArm(ctypes.Structure):
('cc', ctypes.c_uint),
('update_flags', ctypes.c_bool),
('writeback', ctypes.c_bool),
('post_index', ctypes.c_bool),
('mem_barrier', ctypes.c_int),
('op_count', ctypes.c_uint8),
('operands', ArmOp * 36),
)

def get_arch_info(a):
return (a.usermode, a.vector_size, a.vector_data, a.cps_mode, a.cps_flag, a.cc, a.update_flags, \
a.writeback, a.mem_barrier, copy_ctypes_list(a.operands[:a.op_count]))
a.writeback, a.post_index, a.mem_barrier, copy_ctypes_list(a.operands[:a.op_count]))

3 changes: 2 additions & 1 deletion bindings/python/capstone/arm64.py
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Original file line number Diff line number Diff line change
Expand Up @@ -93,10 +93,11 @@ class CsArm64(ctypes.Structure):
('cc', ctypes.c_uint),
('update_flags', ctypes.c_bool),
('writeback', ctypes.c_bool),
('post_index', ctypes.c_bool),
('op_count', ctypes.c_uint8),
('operands', Arm64Op * 8),
)

def get_arch_info(a):
return (a.cc, a.update_flags, a.writeback, copy_ctypes_list(a.operands[:a.op_count]))
return (a.cc, a.update_flags, a.writeback, a.post_index, copy_ctypes_list(a.operands[:a.op_count]))

4 changes: 2 additions & 2 deletions bindings/python/pyx/ccapstone.pyx
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Original file line number Diff line number Diff line change
Expand Up @@ -23,10 +23,10 @@ class CsDetail(object):

if arch == capstone.CS_ARCH_ARM:
(self.usermode, self.vector_size, self.vector_data, self.cps_mode, self.cps_flag, \
self.cc, self.update_flags, self.writeback, self.mem_barrier, self.operands) = \
self.cc, self.update_flags, self.writeback, self.post_index, self.mem_barrier, self.operands) = \
arm.get_arch_info(detail.arch.arm)
elif arch == capstone.CS_ARCH_ARM64:
(self.cc, self.update_flags, self.writeback, self.operands) = \
(self.cc, self.update_flags, self.writeback, self.post_index, self.operands) = \
arm64.get_arch_info(detail.arch.arm64)
elif arch == capstone.CS_ARCH_X86:
(self.prefix, self.opcode, self.rex, self.addr_size, \
Expand Down
5 changes: 4 additions & 1 deletion bindings/python/test_arm.py
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Original file line number Diff line number Diff line change
Expand Up @@ -95,7 +95,10 @@ def print_insn_detail(insn):
if insn.update_flags:
print("\tUpdate-flags: True")
if insn.writeback:
print("\tWrite-back: True")
if insn.post_index:
print("\tWrite-back: Post")
else:
print("\tWrite-back: Pre")
if not insn.cc in [ARM_CC_AL, ARM_CC_INVALID]:
print("\tCode condition: %u" % insn.cc)
if insn.cps_mode:
Expand Down
6 changes: 5 additions & 1 deletion bindings/python/test_arm64.py
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Original file line number Diff line number Diff line change
Expand Up @@ -95,7 +95,11 @@ def print_insn_detail(insn):


if insn.writeback:
print("\tWrite-back: True")
if insn.post_index:
print("\tWrite-back: Post")
else:
print("\tWrite-back: Pre")

if not insn.cc in [ARM64_CC_AL, ARM64_CC_INVALID]:
print("\tCode-condition: %u" % insn.cc)
if insn.update_flags:
Expand Down
1 change: 1 addition & 0 deletions include/capstone/arm.h
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Expand Up @@ -446,6 +446,7 @@ typedef struct cs_arm {
arm_cc cc; ///< conditional code for this insn
bool update_flags; ///< does this insn update flags?
bool writeback; ///< does this insn write-back?
bool post_index; ///< only set if writeback is 'True', if 'False' pre-index, otherwise post.
arm_mem_barrier mem_barrier; ///< Option for some memory barrier instructions

/// Number of operands of this instruction,
Expand Down
1 change: 1 addition & 0 deletions include/capstone/arm64.h
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Expand Up @@ -1798,6 +1798,7 @@ typedef struct cs_arm64 {
arm64_cc cc; ///< conditional code for this insn
bool update_flags; ///< does this insn update flags?
bool writeback; ///< does this insn request writeback? 'True' means 'yes'
bool post_index; ///< only set if writeback is 'True', if 'False' pre-index, otherwise post.

/// Number of operands of this instruction,
/// or 0 when instruction has no operand.
Expand Down
22 changes: 20 additions & 2 deletions tests/test_arm64.c
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Expand Up @@ -131,7 +131,7 @@ static void print_insn_detail(cs_insn *ins)
printf("\tUpdate-flags: True\n");

if (arm64->writeback)
printf("\tWrite-back: True\n");
printf("\tWrite-back: %s\n", arm64->post_index ? "Post" : "Pre");

if (arm64->cc)
printf("\tCode-condition: %u\n", arm64->cc);
Expand Down Expand Up @@ -162,7 +162,25 @@ static void print_insn_detail(cs_insn *ins)

static void test()
{
#define ARM64_CODE "\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c"
#define ARM64_CODE "\x09\x00\x38\xd5" \
"\xbf\x40\x00\xd5" \
"\x0c\x05\x13\xd5" \
"\x20\x50\x02\x0e" \
"\x20\xe4\x3d\x0f" \
"\x00\x18\xa0\x5f" \
"\xa2\x00\xae\x9e" \
"\x9f\x37\x03\xd5" \
"\xbf\x33\x03\xd5" \
"\xdf\x3f\x03\xd5" \
"\x21\x7c\x02\x9b" \
"\x21\x7c\x00\x53" \
"\x00\x40\x21\x4b" \
"\xe1\x0b\x40\xb9" \
"\x20\x04\x81\xda" \
"\x20\x08\x02\x8b" \
"\x10\x5b\xe8\x3c" \
"\xfd\x7b\xba\xa9" \
"\xfd\xc7\x43\xf8"

struct platform platforms[] = {
{
Expand Down