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Remove tPOP and tPUSH as real isntructions. #39

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Remove tPOP and tPUSH as real isntructions. #39

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29 changes: 0 additions & 29 deletions llvm/lib/Target/ARM/ARMInstrThumb.td
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Original file line number Diff line number Diff line change
Expand Up @@ -874,27 +874,6 @@ def : InstAlias<"ldm${p} $Rn!, $regs",
(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs), 0>,
Requires<[IsThumb, IsThumb1Only]>;

let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1,
variadicOpsAreDefs = 1 in
def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
IIC_iPop,
"pop${p}\t$regs", []>,
T1Misc<{1,1,0,?,?,?,?}>, Sched<[WriteLd]> {
bits<16> regs;
let Inst{8} = regs{15};
let Inst{7-0} = regs{7-0};
}

let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
IIC_iStore_m,
"push${p}\t$regs", []>,
T1Misc<{0,1,0,?,?,?,?}>, Sched<[WriteST]> {
bits<16> regs;
let Inst{8} = regs{14};
let Inst{7-0} = regs{7-0};
}

//===----------------------------------------------------------------------===//
// Arithmetic Instructions.
//
Expand Down Expand Up @@ -1741,14 +1720,6 @@ def tLDRpci_pic : PseudoInst<(outs tGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
imm:$cp))]>,
Requires<[IsThumb, IsThumb1Only]>;

// Pseudo-instruction for merged POP and return.
// FIXME: remove when we have a way to marking a MI with these properties.
let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
hasExtraDefRegAllocReq = 1 in
def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
2, IIC_iPop_Br, [],
(tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>;

// Indirect branch using "mov pc, $Rm"
let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
Expand Down
8 changes: 8 additions & 0 deletions llvm/lib/Target/ARM/ARMInstrThumb2.td
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Expand Up @@ -5104,6 +5104,14 @@ def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>;
def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;
def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>;

// Pseudo-instruction for merged POP and return.
// FIXME: remove when we have a way to marking a MI with these properties.
let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
hasExtraDefRegAllocReq = 1 in
def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
2, IIC_iPop_Br, [],
(t2LDMIA_UPD SP SP, pred:$p, reglist:$regs)>, Sched<[WriteBrL]>;

// STMIA/STMIA_UPD aliases w/o the optional .w suffix
def : t2InstAlias<"stm${p} $Rn, $regs",
(t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>;
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/ARM/ARMScheduleA57.td
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Original file line number Diff line number Diff line change
Expand Up @@ -590,7 +590,7 @@ def : InstRW<[A57WriteLDM], (instregex "(t|t2|sys)?LDM(IA|DA|DB|IB)$")>;

// TODO: no writeback latency defined in documentation (implemented as 1 cyc)
def : InstRW<[A57WriteLDM_Upd],
(instregex "(t|t2|sys)?LDM(IA_UPD|DA_UPD|DB_UPD|IB_UPD|IA_RET)", "tPOP")>;
(instregex "(t|t2|sys)?LDM(IA_UPD|DA_UPD|DB_UPD|IB_UPD|IA_RET)")>;

def : InstRW<[A57Write_5cyc_1L], (instregex "VLLDM")>;

Expand Down Expand Up @@ -710,7 +710,7 @@ def A57WriteSTM_Upd : SchedWriteVariant<[

def : InstRW<[A57WriteSTM], (instregex "(t2|sys|t)?STM(IA|DA|DB|IB)$")>;
def : InstRW<[A57WrBackOne, A57WriteSTM_Upd],
(instregex "(t2|sys|t)?STM(IA_UPD|DA_UPD|DB_UPD|IB_UPD)", "tPUSH")>;
(instregex "(t2|sys|t)?STM(IA_UPD|DA_UPD|DB_UPD|IB_UPD)")>;

def : InstRW<[A57Write_5cyc_1S], (instregex "VLSTM")>;

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/ARM/ARMScheduleM55.td
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Expand Up @@ -163,7 +163,7 @@ def : InstRW<[M55WriteDX_DI], (instregex "t2SETPAN$", "tADC$", "tADDhirr$",
"tAND$", "tASRri$", "tASRrr$", "tBIC$", "tBKPT$", "tCBNZ$", "tCBZ$",
"tCMNz$", "tCMPhir$", "tCMPi8$", "tCMPr$", "tCPS$", "tEOR$", "tHINT$",
"tHLT$", "tLSLri$", "tLSLrr$", "tLSRri$", "tLSRrr$", "tMOVSr$",
"tMUL$", "tMVN$", "tORR$", "tPICADD$", "tPOP$", "tPUSH$", "tREV$",
"tMUL$", "tMVN$", "tORR$", "tPICADD$", "tREV$",
"tREV16$", "tREVSH$", "tROR$", "tRSB$", "tSBC$", "tSETEND$",
"tSTMIA_UPD$", "tSTRBi$", "tSTRBr$", "tSTRHi$", "tSTRHr$", "tSTRi$",
"tSTRr$", "tSTRspi$", "tSUBrr$", "tSUBspi$", "tSVC$", "tTRAP$",
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/ARM/ARMScheduleM7.td
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Expand Up @@ -244,9 +244,9 @@ def : InstRW<[WriteLd, M7SingleIssue, M7Read_ISS],
def : InstRW<[WriteST, M7SingleIssue, M7Read_ISS],
(instregex "(t|t2)STM(DB|IA)$")>;
def : InstRW<[M7BaseUpdate, WriteLd, M7SingleIssue, M7Read_ISS],
(instregex "(t|t2)LDM(DB|IA)_UPD$", "tPOP")>;
(instregex "(t|t2)LDM(DB|IA)_UPD$")>;
def : InstRW<[M7BaseUpdate, WriteST, M7SingleIssue, M7Read_ISS],
(instregex "(t|t2)STM(DB|IA)_UPD$", "tPUSH")>;
(instregex "(t|t2)STM(DB|IA)_UPD$")>;

// Load/store doubles cannot be dual-issued.

Expand Down
5 changes: 2 additions & 3 deletions llvm/lib/Target/ARM/ARMScheduleR52.td
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Original file line number Diff line number Diff line change
Expand Up @@ -482,7 +482,7 @@ def : InstRW<[R52WriteILDM, R52Read_ISS],
def : InstRW<[R52WriteILDM, R52WriteAdr, R52Read_ISS],
(instregex "LDM(IA|DA|DB|IB)_UPD", "(t2|sys|t)LDM(IA|DA|DB|IB)_UPD")>;
def : InstRW<[R52WriteILDM, R52WriteAdr, R52Read_ISS],
(instregex "LDMIA_RET", "(t|t2)LDMIA_RET", "tPOP")>;
(instregex "LDMIA_RET", "(t|t2)LDMIA_RET")>;

// Integer Store, Single Element
def : InstRW<[R52WriteLd, R52Read_ISS, R52Read_EX2],
Expand All @@ -505,8 +505,7 @@ def : InstRW<[R52WriteLd, R52WriteAdr, R52Read_ISS, R52Read_EX2],
def : InstRW<[R52WriteISTM, R52Read_ISS, R52Read_EX2],
(instregex "STM(IB|IA|DB|DA)$", "(t2|sys|t)STM(IB|IA|DB|DA)$")>;
def : InstRW<[R52WriteISTM, R52WriteAdr, R52Read_ISS, R52Read_EX2],
(instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD",
"tPUSH")>;
(instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD")>;

// LDRLIT pseudo instructions, they expand to LDR + PICADD
def : InstRW<[R52WriteLd],
Expand Down
5 changes: 2 additions & 3 deletions llvm/lib/Target/ARM/ARMScheduleSwift.td
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Expand Up @@ -485,7 +485,7 @@ let SchedModel = SwiftModel in {
(instregex /*"t2LDMIA_RET", "tLDMIA_RET", "LDMIA_RET",*/
"LDM(IA|DA|DB|IB)_UPD", "(t2|sys|t)LDM(IA|DA|DB|IB)_UPD")>;
def : InstRW<[SwiftWriteLDMAddrWB, SwiftWriteLM, SwiftWriteP1TwoCycle],
(instregex "LDMIA_RET", "(t|t2)LDMIA_RET", "tPOP")>;
(instregex "LDMIA_RET", "(t|t2)LDMIA_RET")>;
// 4.2.23 Integer Store, Single Element
def : InstRW<[SwiftWriteP2],
(instregex "PICSTR", "STR(i12|rs)", "STRB(i12|rs)", "STRH$", "STREX",
Expand Down Expand Up @@ -534,8 +534,7 @@ let SchedModel = SwiftModel in {
def : InstRW<[SwiftWriteSTM],
(instregex "STM(IB|IA|DB|DA)$", "(t2|sys|t)STM(IB|IA|DB|DA)$")>;
def : InstRW<[SwiftWriteP01OneCycle, SwiftWriteSTM],
(instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD",
"tPUSH")>;
(instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD")>;

// LDRLIT pseudo instructions, they expand to LDR + PICADD
def : InstRW<[SwiftWriteP2ThreeCycle, WriteALU],
Expand Down