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test.rs
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test.rs
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#![allow(
clippy::approx_constant,
clippy::too_many_arguments,
clippy::type_complexity,
clippy::upper_case_acronyms
)]
use alloc::vec::Vec;
#[cfg(feature = "full")]
use {alloc::string::String, std::collections::HashSet};
use capstone_sys::cs_group_type;
use libc::c_uint;
use super::arch::*;
use super::*;
const X86_CODE: &[u8] = b"\x55\x48\x8b\x05\xb8\x13\x00\x00";
const ARM_CODE: &[u8] = b"\x55\x48\x8b\x05\xb8\x13\x00\x00";
// Aliases for group types
const JUMP: cs_group_type::Type = cs_group_type::CS_GRP_JUMP;
const CALL: cs_group_type::Type = cs_group_type::CS_GRP_CALL;
const RET: cs_group_type::Type = cs_group_type::CS_GRP_RET;
const INT: cs_group_type::Type = cs_group_type::CS_GRP_INT;
const IRET: cs_group_type::Type = cs_group_type::CS_GRP_IRET;
/// Used as start address for testing
const START_TEST_ADDR: u64 = 0x1000;
#[test]
fn test_x86_simple() {
match Capstone::new().x86().mode(x86::ArchMode::Mode64).build() {
Ok(cs) => match cs.disasm_all(X86_CODE, START_TEST_ADDR) {
Ok(insns) => {
assert_eq!(insns.len(), 2);
let is: Vec<_> = insns.iter().collect();
#[cfg(feature = "full")]
{
assert_eq!(is[0].mnemonic().unwrap(), "push");
assert_eq!(is[1].mnemonic().unwrap(), "mov");
}
assert_eq!(is[0].address(), START_TEST_ADDR);
assert_eq!(is[1].address(), START_TEST_ADDR + 1);
assert_eq!(is[0].bytes(), b"\x55");
assert_eq!(is[1].bytes(), b"\x48\x8b\x05\xb8\x13\x00\x00");
}
Err(err) => panic!("Couldn't disasm instructions: {}", err),
},
Err(e) => {
panic!("Couldn't create a cs engine: {}", e);
}
}
}
#[test]
fn test_arm_simple() {
match Capstone::new().arm().mode(arm::ArchMode::Arm).build() {
Ok(cs) => match cs.disasm_all(ARM_CODE, START_TEST_ADDR) {
Ok(insns) => {
assert_eq!(insns.len(), 2);
let is: Vec<_> = insns.iter().collect();
#[cfg(feature = "full")]
{
assert_eq!(is[0].mnemonic().unwrap(), "streq");
assert_eq!(is[1].mnemonic().unwrap(), "strheq");
}
assert_eq!(is[0].address(), START_TEST_ADDR);
assert_eq!(is[1].address(), START_TEST_ADDR + 4);
}
Err(err) => panic!("Couldn't disasm instructions: {}", err),
},
Err(e) => {
panic!("Couldn't create a cs engine: {}", e);
}
}
}
#[test]
fn test_arm64_none() {
let cs = Capstone::new()
.arm64()
.mode(arm64::ArchMode::Arm)
.build()
.unwrap();
assert!(cs.disasm_all(ARM_CODE, START_TEST_ADDR).unwrap().is_empty());
}
#[cfg(feature = "full")]
#[test]
fn test_x86_names() {
match Capstone::new().x86().mode(x86::ArchMode::Mode32).build() {
Ok(cs) => {
let reg_id = RegId(1);
match cs.reg_name(reg_id) {
Some(reg_name) => assert_eq!(reg_name, "ah"),
None => panic!("Couldn't get register name"),
}
let insn_id = InsnId(1);
match cs.insn_name(insn_id) {
Some(insn_name) => assert_eq!(insn_name, "aaa"),
None => panic!("Couldn't get instruction name"),
}
assert_eq!(cs.group_name(InsnGroupId(1)), Some(String::from("jump")));
let reg_id = RegId(250);
match cs.reg_name(reg_id) {
Some(_) => panic!("invalid register worked"),
None => {}
}
let insn_id = InsnId(6000);
match cs.insn_name(insn_id) {
Some(_) => panic!("invalid instruction worked"),
None => {}
}
assert_eq!(cs.group_name(InsnGroupId(250)), None);
}
Err(e) => {
panic!("Couldn't create a cs engine: {}", e);
}
}
}
#[test]
fn test_detail_false_fail() {
let mut cs = Capstone::new()
.x86()
.mode(x86::ArchMode::Mode64)
.build()
.unwrap();
cs.set_detail(false).unwrap();
let insns = cs.disasm_all(X86_CODE, START_TEST_ADDR).unwrap();
let insns: Vec<_> = insns.iter().collect();
assert_eq!(cs.insn_detail(insns[0]).unwrap_err(), Error::DetailOff);
assert_eq!(cs.insn_detail(insns[1]).unwrap_err(), Error::DetailOff);
}
#[test]
fn test_skipdata() {
use capstone_sys::x86_insn;
let mut cs = Capstone::new()
.x86()
.mode(x86::ArchMode::Mode64)
.build()
.unwrap();
cs.set_detail(false).unwrap();
cs.set_skipdata(true).unwrap();
let x86_code_skip: &[u8] = b"\x2f\x6c";
let insns = cs.disasm_all(x86_code_skip, 0x1000).unwrap();
let insns: Vec<_> = insns.iter().collect();
assert_eq!(insns.len(), 2);
assert_eq!(insns[0].id().0, x86_insn::X86_INS_INVALID as u32);
assert_eq!(insns[1].id().0, x86_insn::X86_INS_INSB as u32);
}
#[cfg(feature = "full")]
#[test]
fn test_detail_true() {
let mut cs1 = Capstone::new()
.x86()
.mode(x86::ArchMode::Mode64)
.build()
.unwrap();
cs1.set_detail(true).unwrap();
let cs2 = Capstone::new()
.x86()
.mode(x86::ArchMode::Mode64)
.detail(true)
.build()
.unwrap();
for cs in [cs1, cs2].iter_mut() {
let insns = cs.disasm_all(X86_CODE, START_TEST_ADDR).unwrap();
let insns: Vec<_> = insns.iter().collect();
let insn_group_ids = [
cs_group_type::CS_GRP_JUMP,
cs_group_type::CS_GRP_CALL,
cs_group_type::CS_GRP_RET,
cs_group_type::CS_GRP_INT,
cs_group_type::CS_GRP_IRET,
];
for insn in insns.iter() {
let detail = cs.insn_detail(insn).expect("Unable to get detail");
let groups = detail.groups();
for insn_group_id in &insn_group_ids {
let insn_group = InsnGroupId(*insn_group_id as InsnGroupIdInt);
assert!(!groups.contains(&insn_group));
}
}
}
}
#[allow(unused)]
fn test_instruction_helper(
cs: &Capstone,
insn: &Insn,
mnemonic_name: &str,
bytes: &[u8],
has_default_syntax: bool,
) {
println!("{:?}", insn);
// Check mnemonic
if has_default_syntax && cfg!(feature = "full") {
// insn_name() does not respect current syntax
// does not always match the internal mnemonic
cs.insn_name(insn.id())
.expect("Failed to get instruction name");
}
#[cfg(feature = "full")]
assert_eq!(
mnemonic_name,
insn.mnemonic().expect("Failed to get mnemonic"),
"Did not match contained insn.mnemonic"
);
// Assert instruction bytes match
assert_eq!(bytes, insn.bytes());
}
fn test_instruction_detail_helper<T>(
cs: &Capstone,
insn: &Insn,
info: &DetailedInsnInfo<T>,
has_default_syntax: bool,
) where
T: Into<ArchOperand> + Clone,
{
// Check mnemonic
if has_default_syntax && cfg!(feature = "full") {
// insn_name() does not respect current syntax
// does not always match the internal mnemonic
cs.insn_name(insn.id())
.expect("Failed to get instruction name");
}
#[cfg(feature = "full")]
assert_eq!(
info.mnemonic,
insn.mnemonic().expect("Failed to get mnemonic"),
"Did not match contained insn.mnemonic"
);
// Assert instruction bytes match
assert_eq!(info.bytes, insn.bytes());
let detail = cs.insn_detail(insn).expect("Could not get detail");
let arch_detail = detail.arch_detail();
let arch_ops = arch_detail.operands();
let expected_ops: Vec<_> = info
.operands
.iter()
.map(|expected_op| {
let expected_op: ArchOperand = (*expected_op).clone().into();
expected_op
})
.collect();
assert_eq!(
expected_ops,
arch_ops,
"operands do not match for \"{}\" (bytes={:02x?})",
insn,
insn.bytes()
);
}
#[cfg(feature = "full")]
/// Assert instruction belongs or does not belong to groups, testing both insn_belongs_to_group
/// and insn_group_ids
fn test_instruction_group_helper<R: Copy + Into<RegId>>(
cs: &Capstone,
insn: &Insn,
mnemonic_name: &str,
bytes: &[u8],
expected_groups: &[cs_group_type::Type],
expected_regs_read: &[R],
expected_regs_write: &[R],
has_default_syntax: bool,
) {
test_instruction_helper(cs, insn, mnemonic_name, bytes, has_default_syntax);
let detail = cs.insn_detail(insn).expect("Unable to get detail");
// Assert expected instruction groups is a subset of computed groups through ids
let instruction_group_ids: HashSet<InsnGroupId> = detail.groups().iter().copied().collect();
let expected_groups_ids: HashSet<InsnGroupId> = expected_groups
.iter()
.map(|&x| InsnGroupId(x as u8))
.collect();
assert!(
expected_groups_ids.is_subset(&instruction_group_ids),
"Expected groups {:?} does NOT match computed insn groups {:?} with ",
expected_groups_ids,
instruction_group_ids
);
// Assert expected instruction groups is a subset of computed groups through enum
let expected_groups_set: HashSet<InsnGroupId> = expected_groups
.iter()
.map(|&x| InsnGroupId(x as u8))
.collect();
assert!(
expected_groups_set.is_subset(&instruction_group_ids),
"Expected groups {:?} does NOT match computed insn groups {:?}",
expected_groups_set,
instruction_group_ids
);
macro_rules! assert_regs_match {
($expected:expr, $actual_regs:expr, $msg:expr) => {{
let mut expected_regs: Vec<RegId> = $expected.iter().map(|&x| x.into()).collect();
expected_regs.sort_unstable();
let mut regs: Vec<RegId> = $actual_regs.iter().map(|&x| x.into()).collect();
regs.sort_unstable();
assert_eq!(expected_regs, regs, $msg);
}};
}
assert_regs_match!(
expected_regs_read,
detail.regs_read(),
"read_regs did not match"
);
assert_regs_match!(
expected_regs_write,
detail.regs_write(),
"write_regs did not match"
);
}
type ExpectedInsns<'a, R> = (
&'a str,
&'a [u8],
&'a [cs_group_type::Type],
&'a [R],
&'a [R],
);
#[allow(unused)]
fn instructions_match_group<R: Copy + Into<RegId>>(
cs: &mut Capstone,
expected_insns: &[ExpectedInsns<R>],
has_default_syntax: bool,
) {
let insns_buf: Vec<u8> = expected_insns
.iter()
.flat_map(|&(_, bytes, _, _, _)| bytes)
.copied()
.collect();
// Details required to get groups information
cs.set_detail(true).unwrap();
let insns = cs
.disasm_all(&insns_buf, START_TEST_ADDR)
.expect("Failed to disassemble");
let insns: Vec<&Insn> = insns.iter().collect();
// Check number of instructions
assert_eq!(insns.len(), expected_insns.len());
#[cfg(feature = "full")]
for (
insn,
&(
expected_mnemonic,
expected_bytes,
expected_groups,
expected_regs_read,
expected_regs_write,
),
) in insns.iter().zip(expected_insns)
{
test_instruction_group_helper(
cs,
insn,
expected_mnemonic,
expected_bytes,
expected_groups,
expected_regs_read,
expected_regs_write,
has_default_syntax,
)
}
}
fn instructions_match(
cs: &mut Capstone,
expected_insns: &[(&str, &[u8])],
has_default_syntax: bool,
) {
let insns_buf: Vec<u8> = expected_insns
.iter()
.flat_map(|&(_, bytes)| bytes)
.copied()
.collect();
// Details required to get groups information
cs.set_detail(true).unwrap();
let insns = cs
.disasm_all(&insns_buf, START_TEST_ADDR)
.expect("Failed to disassemble");
let insns: Vec<_> = insns.iter().collect();
// Check number of instructions
assert_eq!(
insns.len(),
expected_insns.len(),
"Wrong number of instructions"
);
for (insn, &(expected_mnemonic, expected_bytes)) in insns.iter().zip(expected_insns) {
test_instruction_helper(
cs,
insn,
expected_mnemonic,
expected_bytes,
has_default_syntax,
)
}
}
fn instructions_match_detail<T>(
cs: &mut Capstone,
info: &[DetailedInsnInfo<T>],
has_default_syntax: bool,
) where
T: Into<ArchOperand> + Clone,
{
let insns_buf: Vec<u8> = info.iter().flat_map(|info| info.bytes).copied().collect();
// Details required to get groups information
cs.set_detail(true).unwrap();
// todo(tmfink) eliminate check
if info.is_empty() {
// Input was empty, which will cause disasm_all() to fail
return;
}
let insns = cs
.disasm_all(&insns_buf, START_TEST_ADDR)
.expect("Failed to disassemble");
let insns: Vec<_> = insns.iter().collect();
// Check number of instructions
assert_eq!(
insns.len(),
info.len(),
"Number of instructions {} does not match number of provided instruction info structs {}",
insns.len(),
info.len(),
);
for (insn, info) in insns.iter().zip(info) {
test_instruction_detail_helper(cs, insn, info, has_default_syntax)
}
}
#[test]
fn test_instruction_details() {
use crate::arch::x86::X86Reg;
use crate::arch::x86::X86Reg::*;
let expected_insns: &[ExpectedInsns<X86Reg::Type>] = &[
("nop", b"\x90", &[], &[], &[]),
("je", b"\x74\x05", &[JUMP], &[X86_REG_EFLAGS], &[]),
(
"call",
b"\xe8\x28\x07\x00\x00",
&[CALL],
&[X86_REG_RIP, X86_REG_RSP],
&[X86_REG_RSP],
),
("ret", b"\xc3", &[RET], &[X86_REG_RSP], &[X86_REG_RSP]),
("syscall", b"\x0f\x05", &[INT], &[], &[]),
("iretd", b"\xcf", &[IRET], &[], &[]),
("sub", b"\x48\x83\xec\x08", &[], &[], &[X86_REG_EFLAGS]),
("test", b"\x48\x85\xc0", &[], &[], &[X86_REG_EFLAGS]),
("mov", b"\x48\x8b\x05\x95\x4a\x4d\x00", &[], &[], &[]),
("mov", b"\xb9\x04\x02\x00\x00", &[], &[], &[]),
];
let mut cs = Capstone::new()
.x86()
.mode(x86::ArchMode::Mode64)
.build()
.unwrap();
instructions_match_group(&mut cs, expected_insns, true);
}
#[allow(unused)]
fn test_insns_match(cs: &mut Capstone, insns: &[(&str, &[u8])]) {
for &(mnemonic, bytes) in insns.iter() {
let insns = cs.disasm_all(bytes, START_TEST_ADDR).unwrap();
assert_eq!(insns.len(), 1);
#[cfg(feature = "full")]
assert_eq!(insns.iter().next().unwrap().mnemonic(), Some(mnemonic));
}
}
fn test_extra_mode_helper(
arch: Arch,
mode: Mode,
extra_mode: &[ExtraMode],
valid_both_insns: &[(&str, &[u8])],
valid_extra_mode: &[(&str, &[u8])],
) {
let extra_mode = extra_mode.iter().copied();
let mut cs = Capstone::new_raw(arch, mode, extra_mode, None).unwrap();
test_insns_match(&mut cs, valid_both_insns);
for &(_, _) in valid_extra_mode.iter() {
// Capstone will disassemble instructions not allowed by the current mode
// assert!(
// cs.disasm_all(bytes, START_TEST_ADDR).is_err(),
// "Disassembly succeeded when on instruction when it should not have for {:?}",
// bytes);
}
test_insns_match(&mut cs, valid_both_insns);
test_insns_match(&mut cs, valid_extra_mode);
}
#[test]
fn test_extra_mode() {
test_extra_mode_helper(
Arch::ARM,
Mode::Arm,
&[ExtraMode::V8],
&[("str", b"\x04\xe0\x2d\xe5")],
&[("vcvtt.f64.f16", b"\xe0\x3b\xb2\xee")],
);
}
fn test_arch_mode_endian_insns(
cs: &mut Capstone,
arch: Arch,
mode: Mode,
endian: Option<Endian>,
extra_mode: &[ExtraMode],
insns: &[(&str, &[u8])],
) {
let expected_insns: Vec<(&str, &[u8])> = insns
.iter()
.map(|&(mnemonic, bytes)| (mnemonic, bytes))
.collect();
let mut cs_raw = Capstone::new_raw(arch, mode, extra_mode.iter().copied(), endian).unwrap();
let mut cs_raw_endian_set =
Capstone::new_raw(arch, mode, extra_mode.iter().copied(), None).unwrap();
if let Some(some_endian) = endian {
cs_raw_endian_set
.set_endian(some_endian)
.expect("Failed to set endianness");
}
instructions_match(cs, expected_insns.as_slice(), true);
instructions_match(&mut cs_raw, expected_insns.as_slice(), true);
instructions_match(&mut cs_raw_endian_set, expected_insns.as_slice(), true);
}
#[allow(unused)]
#[derive(Copy, Clone)]
#[cfg_attr(feature = "full", derive(Debug))]
struct DetailedInsnInfo<'a, T: 'a + Into<ArchOperand>> {
pub mnemonic: &'a str,
pub bytes: &'a [u8],
pub operands: &'a [T],
}
#[allow(clippy::upper_case_acronyms)]
type DII<'a, T> = DetailedInsnInfo<'a, T>;
impl<'a, T> DetailedInsnInfo<'a, T>
where
T: Into<ArchOperand>,
{
fn new(mnemonic: &'a str, bytes: &'a [u8], operands: &'a [T]) -> DetailedInsnInfo<'a, T>
where
T: Into<ArchOperand>,
{
DetailedInsnInfo {
mnemonic,
bytes,
operands,
}
}
}
fn test_arch_mode_endian_insns_detail<T>(
cs: &mut Capstone,
arch: Arch,
mode: Mode,
endian: Option<Endian>,
extra_mode: &[ExtraMode],
insns: &[DetailedInsnInfo<T>],
) where
T: Into<ArchOperand> + Clone,
{
let extra_mode = extra_mode.iter().copied();
let mut cs_raw = Capstone::new_raw(arch, mode, extra_mode, endian).unwrap();
instructions_match_detail(&mut cs_raw, insns, true);
instructions_match_detail(cs, insns, true);
}
#[cfg(feature = "full")]
#[test]
fn test_syntax() {
use crate::arch::x86::X86Reg;
use crate::arch::x86::X86Reg::*;
let expected_insns: &[(
&str,
&str,
&[u8],
&[cs_group_type::Type],
&[X86Reg::Type],
&[X86Reg::Type],
)] = &[
("nop", "nop", b"\x90", &[], &[], &[]),
("je", "je", b"\x74\x05", &[JUMP], &[X86_REG_EFLAGS], &[]),
(
"call",
"callq",
b"\xe8\x28\x07\x00\x00",
&[CALL],
&[X86_REG_RIP, X86_REG_RSP],
&[X86_REG_RSP],
),
(
"ret",
"retq",
b"\xc3",
&[RET],
&[X86_REG_RSP],
&[X86_REG_RSP],
),
("syscall", "syscall", b"\x0f\x05", &[INT], &[], &[]),
("iretd", "iretl", b"\xcf", &[IRET], &[], &[]),
(
"sub",
"subq",
b"\x48\x83\xec\x08",
&[],
&[],
&[X86_REG_EFLAGS],
),
(
"test",
"testq",
b"\x48\x85\xc0",
&[],
&[],
&[X86_REG_EFLAGS],
),
(
"mov",
"movq",
b"\x48\x8b\x05\x95\x4a\x4d\x00",
&[],
&[],
&[],
),
("mov", "movl", b"\xb9\x04\x02\x00\x00", &[], &[], &[]),
];
let expected_insns_intel: Vec<ExpectedInsns<X86Reg::Type>> = expected_insns
.iter()
.map(|&(mnemonic, _, bytes, groups, reads, writes)| {
(mnemonic, bytes, groups, reads, writes)
})
.collect();
let expected_insns_att: Vec<ExpectedInsns<X86Reg::Type>> = expected_insns
.iter()
.map(|&(_, mnemonic, bytes, groups, reads, writes)| {
(mnemonic, bytes, groups, reads, writes)
})
.collect();
let mut cs = Capstone::new()
.x86()
.mode(x86::ArchMode::Mode64)
.syntax(x86::ArchSyntax::Intel)
.build()
.unwrap();
instructions_match_group(&mut cs, &expected_insns_intel, true);
cs.set_syntax(Syntax::Intel).unwrap();
instructions_match_group(&mut cs, &expected_insns_intel, true);
cs.set_syntax(Syntax::Att).unwrap();
instructions_match_group(&mut cs, &expected_insns_att, false);
// In this case, MASM and Intel syntaxes match
cs.set_syntax(Syntax::Masm).unwrap();
instructions_match_group(&mut cs, &expected_insns_intel, false);
}
// @todo(tmfink) test invalid syntax once we check for invalid options
#[test]
fn test_invalid_syntax() {
// These do no support any syntax change
let rules = [(Arch::ARM, Mode::Thumb)];
let syntaxes = [
// Syntax::Intel,
// Syntax::Att,
// Syntax::Masm,
// Syntax::NoRegName,
];
for &(arch, mode) in rules.iter() {
let mut cs = Capstone::new_raw(arch, mode, NO_EXTRA_MODE, None).unwrap();
for &syntax in syntaxes.iter() {
let result = cs.set_syntax(syntax);
assert!(result.is_err(), "Expected Err, got {:?}", result);
}
}
}
// todo(tmfink): enable test once we test for valid modes
#[test]
#[ignore]
fn test_invalid_mode() {
if let Err(err) = Capstone::new_raw(Arch::PPC, Mode::Thumb, NO_EXTRA_MODE, None) {
assert_eq!(err, Error::InvalidMode);
} else {
panic!("Should fail to create given modes");
}
}
#[test]
fn test_capstone_version() {
let (major, minor) = Capstone::lib_version();
println!("Capstone lib version: ({}, {})", major, minor);
assert!(major > 0 && major < 100, "Invalid major version {}", major);
assert!(minor < 500, "Invalid minor version {}", minor);
}
#[test]
fn test_capstone_supports_arch() {
let architectures = vec![
Arch::ARM,
Arch::ARM64,
Arch::MIPS,
Arch::X86,
Arch::PPC,
Arch::SPARC,
Arch::SYSZ,
Arch::XCORE,
// Arch::M68K,
];
println!("Supported architectures");
for arch in architectures {
let supports_arch = Capstone::supports_arch(arch);
println!(" {:?}: {}", arch, if supports_arch { "yes" } else { "no" });
}
}
#[test]
fn test_capstone_is_diet() {
println!("Capstone is diet: {}", Capstone::is_diet());
}
#[test]
fn test_arch_arm() {
test_arch_mode_endian_insns(
&mut Capstone::new()
.arm()
.mode(arm::ArchMode::Arm)
.build()
.unwrap(),
Arch::ARM,
Mode::Arm,
None,
&[],
&[
("bl", b"\xed\xff\xff\xeb"),
("str", b"\x04\xe0\x2d\xe5"),
("andeq", b"\x00\x00\x00\x00"),
("str", b"\xe0\x83\x22\xe5"),
("mcreq", b"\xf1\x02\x03\x0e"),
("mov", b"\x00\x00\xa0\xe3"),
("strb", b"\x02\x30\xc1\xe7"),
("cmp", b"\x00\x00\x53\xe3"),
("setend", b"\x00\x02\x01\xf1"),
("ldm", b"\x05\x40\xd0\xe8"),
("strdeq", b"\xf4\x80\x00\x00"),
],
);
test_arch_mode_endian_insns(
&mut Capstone::new()
.arm()
.mode(arm::ArchMode::Thumb)
.build()
.unwrap(),
Arch::ARM,
Mode::Thumb,
None,
&[],
&[
("bx", b"\x70\x47"),
("blx", b"\x00\xf0\x10\xe8"),
("mov", b"\xeb\x46"),
("sub", b"\x83\xb0"),
("ldr", b"\xc9\x68"),
("cbz", b"\x1f\xb1"),
("wfi", b"\x30\xbf"),
("cpsie.w", b"\xaf\xf3\x20\x84"),
("tbb", b"\xd1\xe8\x00\xf0"),
("movs", b"\xf0\x24"),
("lsls", b"\x04\x07"),
("subs", b"\x1f\x3c"),
("stm", b"\xf2\xc0"),
("movs", b"\x00\x00"),
("mov.w", b"\x4f\xf0\x00\x01"),
("ldr", b"\x46\x6c"),
],
);
test_arch_mode_endian_insns(
&mut Capstone::new()
.arm()
.mode(arm::ArchMode::Thumb)
.build()
.unwrap(),
Arch::ARM,
Mode::Thumb,
None,
&[],
&[
("mov.w", b"\x4f\xf0\x00\x01"),
("pop.w", b"\xbd\xe8\x00\x88"),
("tbb", b"\xd1\xe8\x00\xf0"),
("it", b"\x18\xbf"),
("iteet", b"\xad\xbf"),
("vdupne.8", b"\xf3\xff\x0b\x0c"),
("msr", b"\x86\xf3\x00\x89"),
("msr", b"\x80\xf3\x00\x8c"),
("sxtb.w", b"\x4f\xfa\x99\xf6"),
("vaddw.u16", b"\xd0\xff\xa2\x01"),
],
);
test_arch_mode_endian_insns(
&mut Capstone::new()
.arm()
.mode(arm::ArchMode::Thumb)
.extra_mode([arm::ArchExtraMode::MClass].iter().copied())
.build()
.unwrap(),
Arch::ARM,
Mode::Thumb,
None,
&[ExtraMode::MClass],
&[("mrs", b"\xef\xf3\x02\x80")],
);
test_arch_mode_endian_insns(
&mut Capstone::new()
.arm()
.mode(arm::ArchMode::Arm)
.extra_mode([arm::ArchExtraMode::V8].iter().copied())
.build()
.unwrap(),
Arch::ARM,
Mode::Arm,
None,
&[ExtraMode::V8],
&[
("vcvtt.f64.f16", b"\xe0\x3b\xb2\xee"),
("crc32b", b"\x42\x00\x01\xe1"),
("dmb", b"\x51\xf0\x7f\xf5"),
],
);
}
#[test]
fn test_arch_arm_detail() {
use crate::arch::arm::ArmOperandType::*;
use crate::arch::arm::*;
use capstone_sys::arm_op_mem;
let r0_op = ArmOperand {
op_type: Reg(RegId(ArmReg::ARM_REG_R0 as RegIdInt)),
..Default::default()
};
test_arch_mode_endian_insns_detail(
&mut Capstone::new()
.arm()
.mode(arm::ArchMode::Arm)
.build()
.unwrap(),
Arch::ARM,
Mode::Arm,
Some(Endian::Little),
&[],
&[
// bl #0xfbc
DII::new(
"bl",
b"\xed\xff\xff\xeb",
&[ArmOperand {
op_type: Imm(0xfbc),
..Default::default()
}],
),
// str lr, [sp, #-4]!
DII::new(
"str",
b"\x04\xe0\x2d\xe5",
&[
ArmOperand {
op_type: Reg(RegId(ArmReg::ARM_REG_LR as RegIdInt)),
..Default::default()
},
ArmOperand {
op_type: Mem(ArmOpMem(arm_op_mem {
base: ArmReg::ARM_REG_SP,
index: 0,
scale: 1,
disp: -4,
lshift: 0,
})),
..Default::default()
},
],
),
// andeq r0, r0, r0
DII::new(
"andeq",
b"\x00\x00\x00\x00",
&[r0_op.clone(), r0_op.clone(), r0_op.clone()],
),
// str r8, [r2, #-0x3e0]!
DII::new(
"str",
b"\xe0\x83\x22\xe5",
&[
ArmOperand {
op_type: Reg(RegId(ArmReg::ARM_REG_R8 as RegIdInt)),
..Default::default()
},
ArmOperand {
op_type: Mem(ArmOpMem(arm_op_mem {
base: ArmReg::ARM_REG_R2,
index: 0,
scale: 1,
disp: -992,
lshift: 0,
})),
..Default::default()
},
],
),
// mcreq p2, #0, r0, c3, c1, #7
DII::new(
"mcreq",
b"\xf1\x02\x03\x0e",
&[
ArmOperand {
op_type: Pimm(2),
..Default::default()
},
ArmOperand {
op_type: Imm(0),
..Default::default()
},
r0_op.clone(),
ArmOperand {
op_type: Cimm(3),
..Default::default()
},
ArmOperand {
op_type: Cimm(1),
..Default::default()
},
ArmOperand {
op_type: Imm(7),
..Default::default()
},
],
),
// mov r0, #0
DII::new(
"mov",
b"\x00\x00\xa0\xe3",
&[
r0_op,