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Merge pull request #26 from ska-sa/devel
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casperfpga install bug fix
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jkocz committed Jun 11, 2020
2 parents 8ff98a5 + 3072241 commit 22faafe
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Showing 16 changed files with 1,034 additions and 380 deletions.
2 changes: 1 addition & 1 deletion README.md
Original file line number Diff line number Diff line change
Expand Up @@ -49,7 +49,7 @@ DEBUG:root:casperfpga.casperfpga:roach020203: now a CasperFpga
[`casperfpga`](https://pypi.org/project/casperfpga/) is now available on the Python Package Index (PyPI) and can be installed via [`pip`](https://pip.pypa.io/en/stable/). However, should you need to interface with a SNAP board, your installation workflow involves the extra step of installing against `casperfpga's requirements.txt`.

```shell
$ git clone https://github.com/casper-astro/casperfpga
$ git clone https://github.com/ska-sa/casperfpga
$ cd casperfpga/
$ sudo apt-get install python-pip
$ sudo pip install -r requirements.txt
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16 changes: 6 additions & 10 deletions setup.py
Original file line number Diff line number Diff line change
Expand Up @@ -6,14 +6,12 @@
NAME = 'casperfpga'
DESCRIPTION = 'Talk to CASPER hardware devices using katcp or dcp. See https://github.com/casper-astro/casperfpga for more.'
URL = 'https://github.com/casper-astro/casperfpga'
EMAIL = 'apatel@ska.ac.za'
AUTHOR = 'Paul Prozesky'
VERSION = '0.1.3' # Need to adopt the __version__.py format
AUTHOR = 'Tyrone van Balla'
EMAIL = 'tvanballa at ska.ac.za'


here = os.path.abspath(os.path.dirname(__file__))


try:
with open(os.path.join(here, 'README.md')) as readme:
# long_description = readme.read().split('\n')[2]
Expand Down Expand Up @@ -42,7 +40,6 @@

setuptools.setup(
name=NAME,
version=VERSION,
description=DESCRIPTION,
author=AUTHOR,
author_email=EMAIL,
Expand All @@ -53,18 +50,17 @@
long_description_content_type='text/markdown',
# Specify version in-line here
install_requires=[
'katcp==0.6.2',
'katcp>=0.6.2',
'numpy<1.17',
'odict',
'setuptools',
'tornado<5',
],
packages=['casperfpga', 'casperfpga.progska'],
package_dir={'casperfpga': 'src', 'casperfpga.progska': 'progska'},
package_data={'casperfpga': data_files},
packages=['casperfpga'],
package_dir={'casperfpga': 'src'},
scripts=glob.glob('scripts/*'),
setup_requires=['katversion'],
use_katversion=False,
use_katversion=True,
ext_modules=[progska_extension],
# Required for PyPI
keywords='casper ska meerkat fpga',
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83 changes: 36 additions & 47 deletions src/casperfpga.py
Original file line number Diff line number Diff line change
Expand Up @@ -288,7 +288,7 @@ def set_igmp_version(self, version):
return self.transport.set_igmp_version(version)

def upload_to_ram_and_program(self, filename=None, wait_complete=True,
chunk_size=1988, initialise_objects=False):
initialise_objects=False, **kwargs):
"""
Upload an FPG file to RAM and then program the FPGA.
:param filename: The file to upload
Expand All @@ -299,40 +299,37 @@ def upload_to_ram_and_program(self, filename=None, wait_complete=True,
:param initialise_objects: Flag included in the event some child objects can be initialised
upon creation/startup of the SKARAB with the new firmware
- e.g. The SKARAB ADC
:param **kwargs: chunk_size - set the chunk_size for the SKARAB platform
:return: Boolean - True/False - Success/Fail
"""
if filename is not None:
self.bitstream = filename
else:
filename = self.bitstream

# TODO: only skarab needs chunk_size, and it can break function calls to to other transport layers
# TODO: this is a quick fix for now. A more elegant solution is required.
if self.transport == SkarabTransport:
rv = self.transport.upload_to_ram_and_program(
filename=filename, wait_complete=wait_complete, chunk_size=chunk_size)
else:
rv = self.transport.upload_to_ram_and_program(
filename=filename, wait_complete=wait_complete)
rv = self.transport.upload_to_ram_and_program(
filename=filename, wait_complete=wait_complete, **kwargs)

if not wait_complete:
return True

if self.bitstream:
if self.bitstream[-3:] == 'fpg':
self.get_system_information(filename,
initialise_objects=initialise_objects)
# if the board returned after programming successfully, get_sys_info
if rv:
if self.bitstream:
if self.bitstream[-3:] == 'fpg':
self.get_system_information(filename,
initialise_objects=initialise_objects)

# The Red Pitaya doesn't respect network-endianness. It should.
# For now, detect this board so that an endianness flip can be
# inserted between the CasperFpga and the underlying transport layer
# This check is in upload_to_ram and program because if we connected
# to a board that wasn't programmed the detection in __init__ won't have worked.
try:
self._detect_little_endianness()
except:
pass

# The Red Pitaya doesn't respect network-endianness. It should.
# For now, detect this board so that an endianness flip can be
# inserted between the CasperFpga and the underlying transport layer
# This check is in upload_to_ram and program because if we connected
# to a board that wasn't programmed the detection in __init__ won't have worked.
try:
self._detect_little_endianness()
except:
pass

def is_connected(self, **kwargs):
"""
Expand Down Expand Up @@ -574,7 +571,7 @@ def write_int(self, device_name, integer, blindwrite=False, word_offset=0):
'okay%s.' % (integer, device_name, word_offset,
' (blind)' if blindwrite else ''))

def _create_memory_devices(self, device_dict, memorymap_dict, legacy_reg_map=True, **kwargs):
def _create_memory_devices(self, device_dict, memorymap_dict, **kwargs):
"""
Create memory devices from dictionaries of design information.
Expand All @@ -583,6 +580,7 @@ def _create_memory_devices(self, device_dict, memorymap_dict, legacy_reg_map=Tru
:param memorymap_dict: dictionary of information that would have been
in coreinfo.tab - memory bus information
"""

# create and add memory devices to the memory device dictionary
for device_name, device_info in device_dict.items():
if device_name == '':
Expand All @@ -601,8 +599,10 @@ def _create_memory_devices(self, device_dict, memorymap_dict, legacy_reg_map=Tru
if not callable(known_device_class):
raise TypeError('%s is not a callable Memory class - '
'that\'s a problem.' % known_device_class)

new_device = known_device_class.from_device_info(
self, device_name, device_info, memorymap_dict, legacy_reg_map=legacy_reg_map)
self, device_name, device_info, memorymap_dict)

if new_device.name in self.memory_devices.keys():
raise NameError(
'Device called %s of type %s already exists in '
Expand Down Expand Up @@ -744,33 +744,22 @@ def get_system_information(self, filename=None, fpg_info=None,
# and RCS information if included
for device_name in device_dict:
if device_name.startswith('77777_git'):
name = device_name[device_name.find('_', 10) + 1:]
if 'git' not in self.rcs_info:
self.rcs_info['git'] = {}
self.rcs_info['git'][name] = device_dict[device_name]

if '77777_svn' in device_dict:
self.rcs_info['svn'] = device_dict['77777_svn']

legacy_reg_map = False
if type(self.transport) is SkarabTransport:
# Determine if the new or old register map is used
new_reg_map_mac_word1_hex = self.transport.read_wishbone(0x54000 + 0x03 * 4)
old_reg_map_mac_word1_hex = self.transport.read_wishbone(0x54000 + 0x00 * 4)

if(new_reg_map_mac_word1_hex == 0x650):
self.logger.debug('Using new 40GbE core register map')
legacy_reg_map = False
elif(old_reg_map_mac_word1_hex == 0x650):
self.logger.debug('Using old 40GbE core register map')
legacy_reg_map = True
else:
self.logger.error('Unknown 40GbE core register map')
raise ValueError('Unknown register map')
self.rcs_info['git'].update(device_dict[device_name])

if device_name.startswith('77777_svn'):
if 'svn' not in self.rcs_info:
self.rcs_info['svn'] = {}
self.rcs_info['svn'].update(device_dict[device_name])

try:
self.rcs_info['git'].pop('tag')
except:
pass

# Create Register Map
self._create_memory_devices(device_dict, memorymap_dict,
legacy_reg_map=legacy_reg_map,
initialise=initialise_objects)
self._create_other_devices(device_dict, initialise=initialise_objects)
self._create_casper_adc_devices(device_dict, initialise=initialise_objects)
Expand Down

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