frame_sync: add reconnect_mode (#26)

catkira · Jun 2, 2023 · 41c1d90 · 41c1d90
1 parent bfcc055
commit 41c1d90
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Showing 2 changed files with 43 additions and 4 deletions.
diff --git a/hdl/frame_sync.sv b/hdl/frame_sync.sv
@@ -118,6 +118,34 @@ always @(posedge clk_i) begin
     else ibar_SSB <= ibar_SSB_valid_i ? ibar_SSB_i : ibar_SSB;
 end
 
+
+// ---------------------------------------------------------------------------------------------------//
+// FSM for controlling reconnect_mode
+wire reconnect_mode_write;
+wire [1 : 0] reconnect_mode_regmap;
+reg [1 : 0] reconnect_mode;
+localparam [1 : 0] RECONNECT_MODE_AUTO = 0;
+localparam [1 : 0] RECONNECT_MODE_ONCE = 1;
+localparam [1 : 0] RECONNECT_MODE_WAIT = 2;
+always @(posedge clk_i) begin
+    if (!reset_ni)         reconnect_mode <= RECONNECT_MODE_AUTO;
+    else begin
+        case (reconnect_mode)
+            RECONNECT_MODE_AUTO : begin
+                if (reconnect_mode_write) reconnect_mode <= reconnect_mode_regmap;
+            end
+            RECONNECT_MODE_ONCE : begin
+                if (N_id_2_valid_i) reconnect_mode <= RECONNECT_MODE_WAIT;
+                else if (reconnect_mode_write) reconnect_mode <= reconnect_mode_regmap;
+            end
+            RECONNECT_MODE_WAIT : begin 
+                if (reconnect_mode_write) reconnect_mode <= reconnect_mode_regmap;
+            end
+            default: begin end
+        endcase
+    end
+end
+
 // ---------------------------------------------------------------------------------------------------//
 // FSM for controlling PSS detector
 localparam [1 : 0] PSS_DETECTOR_MODE_SEARCH = 0;
@@ -143,7 +171,7 @@ always @(posedge clk_i) begin
         PSS_detector_mode_o <= PSS_state;
         case (PSS_state)
             SEARCH_PSS : begin  // search PSS with any N_id_2
-                if (N_id_2_valid_i) begin
+                if (N_id_2_valid_i && (reconnect_mode != RECONNECT_MODE_WAIT)) begin
                     missed_SSBs <= '0;
                     PSS_state <= PAUSE_PSS;
                     clks_since_SSB <= 1;
@@ -173,6 +201,7 @@ always @(posedge clk_i) begin
                     clks_since_SSB <= clks_since_SSB + 1;
                 end
             end
+            default : begin end
         endcase
     end
 end
@@ -271,7 +300,7 @@ always @(posedge clk_i) begin
             WAIT_FOR_SSB: begin
                 SSB_start_o <= '0;
                 find_SSB <= '0;                
-                if (N_id_2_valid_i) begin
+                if (N_id_2_valid_i && (reconnect_mode != RECONNECT_MODE_WAIT)) begin
                     sample_cnt <= 0;
                     out_valid <= s_axis_in_tvalid;
                     // SSB_pattern for case A is [2, 8, 16, 22]
@@ -419,6 +448,10 @@ frame_sync_regmap_i(
     .ibar_SSB_i(ibar_SSB),
     .clks_btwn_SSBs_i(clks_since_SSB_f),
     .num_disconnects_i(num_disconnects),
+    .reconnect_mode_i(reconnect_mode),
+
+    .reconnect_mode_o(reconnect_mode_regmap),
+    .reconnect_mode_write_o(reconnect_mode_write),
 
     .s_axi_if_awaddr(s_axi_awaddr),
     .s_axi_if_awvalid(s_axi_awvalid),

diff --git a/hdl/frame_sync_regmap.sv b/hdl/frame_sync_regmap.sv
@@ -57,7 +57,11 @@ module frame_sync_regmap #(
     input           [15 : 0]                    missed_SSBs_i,
     input           [2 : 0]                     ibar_SSB_i,
     input           [31 : 0]                    clks_btwn_SSBs_i,
-    input           [31 : 0]                    num_disconnects_i
+    input           [31 : 0]                    num_disconnects_i,
+    input           [1 : 0]                     reconnect_mode_i,
+
+    output                                      reconnect_mode_write_o,
+    output          [1 : 0]                     reconnect_mode_o
 );
 
 localparam PCORE_VERSION = 'h00010061; // 1.0.a
@@ -83,7 +87,7 @@ always @(posedge clk_i) begin
                 9'h003: rdata <= 32'h46537E7E; // "FS~~"
                 9'h004: rdata <= 32'h69696969;
                 9'h005: rdata <= {30'd0, fs_state_i};
-                9'h006: rdata <= '0;
+                9'h006: rdata <= {30'd0, reconnect_mode_i};
                 9'h007: rdata <= '0;
                 9'h008: rdata <= '0;
                 9'h009: rdata <= {24'd0, sample_cnt_mismatch_i};
@@ -108,6 +112,8 @@ always @(posedge clk_i) begin
     else            wack <= wreq;   // ack immediately after req
 end
 
+assign reconnect_mode_write_o = wreq && (waddr == 9'h006);
+assign reconnect_mode_o = wdata[1 : 0];
 always @(posedge clk_i) begin
     if (!reset_ni) begin
     end else begin