rename SSB_extractor to BWP_extractor

catkira · May 25, 2023 · 7e209fe · 7e209fe
1 parent c786e2a
commit 7e209fe
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Showing 5 changed files with 23 additions and 95 deletions.
diff --git a/hdl/Decimator_Correlator_PeakDetector_FFT.sv b/hdl/Decimator_Correlator_PeakDetector_FFT.sv
@@ -155,12 +155,12 @@ FFT_demod_i(
     .m_axis_out_tvalid(fft_demod_out_tvalid)
 );
 
-SSB_extractor #(
+BWP_extractor #(
     .IN_DW(FFT_OUT_DW),
     .NFFT(NFFT),
     .BLK_EXP_LEN(BLK_EXP_LEN)
 )
-SSB_extractor_i(
+BWP_extractor_i(
     .clk_i(clk_i),
     .reset_ni(reset_ni),
 

diff --git a/hdl/SSB_extractor.sv b/hdl/SSB_extractor.sv
diff --git a/hdl/receiver.sv b/hdl/receiver.sv
@@ -618,18 +618,18 @@ FFT_demod_i(
     .m_axis_out_tvalid(fft_demod_out_tvalid)
 );
 
-wire [FFT_OUT_DW - 1 : 0] ssb_tdata;
-wire ssb_tvalid;
-assign m_axis_demod_out_tdata = ssb_tdata;
-assign m_axis_demod_out_tvalid = ssb_tvalid;
-wire [FFT_DEMOD_OUT_USER_WIDTH - 1 : 0] ssb_tuser;
+wire [FFT_OUT_DW - 1 : 0] bwp_tdata;
+wire bwp_tvalid;
+assign m_axis_demod_out_tdata = bwp_tdata;
+assign m_axis_demod_out_tvalid = bwp_tvalid;
+wire [FFT_DEMOD_OUT_USER_WIDTH - 1 : 0] bwp_tuser;
 wire ssb_tlast;
-SSB_extractor #(
+BWP_extractor #(
     .IN_DW(FFT_OUT_DW),
     .NFFT(NFFT),
     .BLK_EXP_LEN(BLK_EXP_LEN)
 )
-SSB_extractor_i(
+BWB_extractor_i(
     .clk_i(clk_i),
     .reset_ni(reset_fft_demod_n),
 
@@ -638,10 +638,10 @@ SSB_extractor_i(
     .s_axis_in_tvalid(fft_demod_out_tvalid),
     .s_axis_in_tlast(fft_demod_out_tlast),
 
-    .m_axis_out_tdata(ssb_tdata),
-    .m_axis_out_tuser(ssb_tuser),
-    .m_axis_out_tvalid(ssb_tvalid),
-    .m_axis_out_tlast(ssb_tlast),
+    .m_axis_out_tdata(bwp_tdata),
+    .m_axis_out_tuser(bwp_tuser),
+    .m_axis_out_tvalid(bwp_tvalid),
+    .m_axis_out_tlast(bwp_tlast),
     .PBCH_valid_o(PBCH_valid_o),
     .SSS_valid_o(SSS_valid_o)
 );
@@ -655,10 +655,10 @@ ressource_grid_subscriber_i(
     .clk_i(clk_i),
     .reset_ni(reset_fft_demod_n),
 
-    .s_axis_iq_tdata(ssb_tdata),
-    .s_axis_iq_tuser(ssb_tuser),
-    .s_axis_iq_tvalid(ssb_tvalid),
-    .s_axis_iq_tlast(ssb_tlast),
+    .s_axis_iq_tdata(bwp_tdata),
+    .s_axis_iq_tuser(bwp_tuser),
+    .s_axis_iq_tvalid(bwp_tvalid),
+    .s_axis_iq_tlast(bwp_tlast),
 
     .sample_id_data(sample_id_fifo_out_data),
     .sample_id_valid(sample_id_fifo_out_valid),
@@ -678,7 +678,7 @@ SSS_detector_i(
     .reset_ni(reset_fft_demod_n),
     .N_id_2_i(fs_N_id_2),
     .N_id_2_valid_i(fs_N_id_2_valid),
-    .s_axis_in_tdata(ssb_tdata),
+    .s_axis_in_tdata(bwp_tdata),
     .s_axis_in_tvalid(SSS_valid_o),
     .m_axis_out_tdata(m_axis_SSS_tdata),
     .m_axis_out_tvalid(m_axis_SSS_tvalid),
@@ -698,9 +698,9 @@ channel_estimator_i(
     .reset_ni(reset_fft_demod_n),
     .N_id_i(N_id),
     .N_id_valid_i(N_id_valid),
-    .s_axis_in_tdata(ssb_tdata),
-    .s_axis_in_tuser(ssb_tuser[BLK_EXP_LEN + 1 - 1 : 0]),
-    .s_axis_in_tvalid(ssb_tvalid),
+    .s_axis_in_tdata(bwp_tdata),
+    .s_axis_in_tuser(bwp_tuser[BLK_EXP_LEN + 1 - 1 : 0]),
+    .s_axis_in_tvalid(bwp_tvalid),
 
     .m_axis_out_tdata(m_axis_cest_out_tdata),
     .m_axis_out_tuser(m_axis_cest_out_tuser),

diff --git a/tests/test_Decimator_Correlator_PeakDetector_FFT.py b/tests/test_Decimator_Correlator_PeakDetector_FFT.py
@@ -325,7 +325,7 @@ def test(IN_DW, OUT_DW, TAP_DW, ALGO, WINDOW_LEN, HALF_CP_ADVANCE, NFFT, USE_TAP
         os.path.join(rtl_dir, 'FFT/buffers/outbuf_half_path.v'),
         os.path.join(rtl_dir, 'FFT/buffers/int_bitrev_order.v'),
         os.path.join(rtl_dir, 'FFT/buffers/dynamic_block_scaling.v'),
-        os.path.join(rtl_dir, 'SSB_extractor.sv')
+        os.path.join(rtl_dir, 'BWP_extractor.sv')
     ]
     if os.environ.get('SIM') != 'verilator':
         verilog_sources.append(os.path.join(rtl_dir, '../submodules/FFT/submodules/XilinxUnisimLibrary/verilog/src/glbl.v'))

diff --git a/tests/test_receiver.py b/tests/test_receiver.py
@@ -515,7 +515,7 @@ def test(IN_DW, OUT_DW, TAP_DW, WINDOW_LEN, CFO, HALF_CP_ADVANCE, USE_TAP_FILE,
         os.path.join(rtl_dir, 'FFT/buffers/int_bitrev_order.v'),
         os.path.join(rtl_dir, 'FFT/buffers/dynamic_block_scaling.v'),
         os.path.join(rtl_dir, 'ressource_grid_subscriber.sv'),
-        os.path.join(rtl_dir, 'SSB_extractor.sv'),
+        os.path.join(rtl_dir, 'BWP_extractor.sv'),
     ]
     if os.environ.get('SIM') != 'verilator':
         verilog_sources.append(os.path.join(rtl_dir, '../submodules/FFT/submodules/XilinxUnisimLibrary/verilog/src/glbl.v'))