remove unused symbol_start_o output of frame_sync

catkira · Jul 13, 2023 · fa46efb · fa46efb
1 parent 08e762f
commit fa46efb
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Showing 3 changed files with 8 additions and 41 deletions.
diff --git a/hdl/frame_sync.sv b/hdl/frame_sync.sv
@@ -42,7 +42,6 @@ module frame_sync #(
     output  reg        [USER_WIDTH - 1 : 0]         m_axis_out_tuser,
     output  reg                                     m_axis_out_tlast,
     output  reg                                     m_axis_out_tvalid,
-    output  reg                                     symbol_start_o,
     output  reg                                     SSB_start_o,
     output  reg                                     reset_fft_no,
     output  reg        [1 : 0]                      N_id_2_o,
@@ -276,7 +275,7 @@ wire end_of_symbol_ = sample_cnt == (FFT_LEN + current_CP_len - 1);
 
 // manual timing_advance can happend at the end of a subframe
 reg signed [31 : 0] timing_advance;
-wire do_manual_ta = ((sym_cnt == SYM_PER_SF - 1) && ((sample_cnt == (FFT_LEN + current_CP_len - 1) + timing_advance) && timing_advance_queued));
+wire do_manual_ta = ((sym_cnt == SYM_PER_SF - 1) && ((sample_cnt == FFT_LEN + current_CP_len - 1 + timing_advance) && timing_advance_queued));
 wire end_of_symbol_ta_manual = (timing_advance_mode == TA_MODE_MANUAL) && 
     (do_manual_ta || (end_of_symbol_ && (!timing_advance_queued || (sym_cnt != SYM_PER_SF - 1))));
 
@@ -306,7 +305,7 @@ always @(posedge clk_i) begin
     end else if(timing_advance_write) begin
         timing_advance <= timing_advance_regmap;
         timing_advance_queued <= 1;
-    end else if(end_of_symbol_ta_manual && (sym_cnt == SYM_PER_SF - 1))
+    end else if(end_of_symbol_ta_manual && do_manual_ta)
         timing_advance_queued <= '0;
 end
 
@@ -435,42 +434,6 @@ always @(posedge clk_i) begin
     end
 end
 
-// ----------------------------------------------------------------
-// This process sets symbol_start_o to 1 at the beginning of every symbol,
-// but only when the FSM above is in SYNCED state
-reg symbol_state;
-always @(posedge clk_i) begin
-    if (!reset_ni) begin
-        symbol_start_o <= '0;
-        symbol_state <= '0;
-    end else begin
-        case (symbol_state)
-            0: begin
-                // first symbol of SSB can arrive a bit earlier or later,
-                // therefore need a special check for this case
-                if (find_SSB) begin
-                    if ((state != WAIT_FOR_SSB) && N_id_2_valid_i) begin
-                        symbol_state <= 1;
-                        symbol_start_o <= 1;
-                    end
-                end else begin
-                    if ((state != WAIT_FOR_SSB) && (sample_cnt == 0) && (s_axis_in_tvalid)) begin
-                        symbol_state <= 1;
-                        symbol_start_o <= 1;
-                    end
-                end
-            end
-            1: begin
-                symbol_start_o <= '0;
-                if ((sample_cnt == 1) || (state == WAIT_FOR_SSB)) symbol_state <= '0;
-            end
-        endcase
-    end
-end
-
-// store sample_id into FIFO at the beginning of each symbol
-assign sample_id_valid = symbol_start_o;
-
 frame_sync_regmap #(
     .ID(0),
     .ADDRESS_WIDTH(AXI_ADDRESS_WIDTH)
@@ -493,6 +456,8 @@ frame_sync_regmap_i(
     .timing_advance_write_o(timing_advance_write),
     .timing_advance_o(timing_advance_regmap),
     .timing_advance_mode_o(timing_advance_mode),
+    .timing_advance_i(timing_advance),
+    .timing_advance_queued_i(timing_advance_queued),
 
     .s_axi_if_awaddr(s_axi_awaddr),
     .s_axi_if_awvalid(s_axi_awvalid),

diff --git a/hdl/frame_sync_regmap.sv b/hdl/frame_sync_regmap.sv
@@ -60,6 +60,8 @@ module frame_sync_regmap #(
     input           [31 : 0]                    num_disconnects_i,
     input           [1 : 0]                     reconnect_mode_i,
     input                                       rgf_overflow_i,
+    input           [31 : 0]                    timing_advance_i,
+    input                                       timing_advance_queued_i,
 
     output                                      reconnect_mode_write_o,
     output          [1 : 0]                     reconnect_mode_o,
@@ -100,7 +102,9 @@ always @(posedge clk_i) begin
                 9'h00C: rdata <= clks_btwn_SSBs_i;
                 9'h00D: rdata <= num_disconnects_i;
                 9'h00E: rdata <= '0;
+                9'h010: rdata <= timing_advance_i;
                 9'h011: rdata <= {31'd0, timing_advance_mode_o};
+                9'h012: rdata <= timing_advance_queued_i;
                 default: rdata <= '0;
             endcase
         end

diff --git a/hdl/receiver.sv b/hdl/receiver.sv
@@ -519,7 +519,6 @@ reg [IN_DW - 1 : 0]     fs_out_tdata;
 reg [USER_WIDTH - 1 : 0] fs_out_tuser;
 reg fs_out_tvalid;
 reg fs_out_SSB_start;
-reg fs_out_symbol_start;
 wire fs_out_tlast;
 wire [2 : 0] ibar_SSB;
 wire ibar_SSB_valid;
@@ -561,7 +560,6 @@ frame_sync_i
     .m_axis_out_tuser(fs_out_tuser),
     .m_axis_out_tlast(fs_out_tlast),
     .m_axis_out_tvalid(fs_out_tvalid),
-    .symbol_start_o(fs_out_symbol_start),
     .SSB_start_o(fs_out_SSB_start),
     .reset_fft_no(reset_fft_n),
     .N_id_2_o(fs_N_id_2),