Current hardware design is dominated by two languages, VHDL and Verilog, which are about 30 years old. They have been originaly not designed for hardware synthesis. Therefore, a lotmof constructs in the language cannot be implemented in hardware and basic synthesizable constructs (combinational logic, refisters, and memory) are are only 'infered' from code in a typical style.
However, several projects take the active development of new languages for classic softwa development and adapt it for hardware description langages (HDL). This GitHub project is about getting an overview what is out on new tools and trying to assess the pro and cons for individual languages.