Merge pull request #60 from aorcajo/master

Renamed async to isasync

.travis.yml

@@ -1,8 +1,10 @@
 # http://docs.travis-ci.com/user/workers/container-based-infrastructure/
 sudo: false
+dist: xenial
 
 language: python
 python:
+  - "3.7"
   - "3.5"
   - "3.4"
   - "2.7"

docs/source/base_building_blocks.rst

@@ -14,7 +14,7 @@ The following is the list of the functions and objects in the rhea
 top-level namespace.  See the information below for more details.
 
    #. rhea.Clock(init_val, frequency)
-   #. rhea.Reset(init_val, active, async)
+   #. rhea.Reset(init_val, active, isasync)
    #. rhea.Global()
    #. rhea.Constants(**named_constants)
    #. rhea.Signals(sigtype, num_sigs)

examples/boards/atlys/test_atlys_blinky_host.py

@@ -20,7 +20,7 @@ def test_ibh(args=None):
     numbytes = 13
 
     clock = Clock(0, frequency=50e6)
-    reset = Reset(0, active=0, async=True)
+    reset = Reset(0, active=0, isasync=True)
     glbl = Global(clock, reset)
     led = Signal(intbv(0)[8:])
     sw = Signal(intbv(1)[8:])

examples/boards/de0nano/button_led/test.py

@@ -16,7 +16,7 @@
 def test_btn_led():
 
     clock = Clock(0, frequency=500e3)
-    reset = Reset(0, active=0, async=False)
+    reset = Reset(0, active=0, isasync=False)
     leds = Signal(intbv(0)[8:])
     btns = Signal(intbv(0)[4:])
 

examples/boards/de0nano/converters/de0nano_converters.py

@@ -102,7 +102,7 @@ def beh_leds():
 #        portmap = brd.map_ports(de0nano_converters)
 de0nano_converters.portmap = {
     'clock': Clock(0, frequency=50e6),
-    'reset': Reset(0, active=0, async=True),
+    'reset': Reset(0, active=0, isasync=True),
     'led': Signal(intbv(0)[8:]),
     'adc_cs_n': Signal(bool(1)),
     'adc_saddr': Signal(bool(1)),

examples/boards/de0nano/lt24lcd/de0nano_lt24lcd.py

@@ -73,7 +73,7 @@ def beh_leds():
 #        portmap = brd.map_ports(de0nano_converters)
 de0nano_lt24lcd.portmap = {
     'clock': Clock(0, frequency=50e6),
-    'reset': Reset(0, active=0, async=True),
+    'reset': Reset(0, active=0, isasync=True),
     'led': Signal(intbv(0)[8:]),
     'lcd_on': Signal(bool(1)),
     'lcd_resetn': Signal(bool(1)),

examples/boards/de0nano_soc/device_primitives/de0nano_soc_device_prims.py

@@ -68,7 +68,7 @@ def beh_assign():
 def test_devprim(args=None):
     args = tb_default_args(args)
     clock = Clock(0, frequency=50e6)
-    reset = Reset(0, active=0, async=True)
+    reset = Reset(0, active=0, isasync=True)
     led = Signal(intbv(0))
 
     @myhdl.block

examples/boards/nexys/fpgalink/fpgalink.py

@@ -99,7 +99,7 @@ def convert():
     FLAGA,FLAGB,FLAGC,FLAGD = [Signal(bool(0)) for _ in range(4)]
     ADDR = Signal(intbv(0)[2:])
     IFCLK = Signal(bool(0))
-    RST = ResetSignal(bool(1), active=0, async=True)
+    RST = ResetSignal(bool(1), active=0, isasync=True)
     LEDS = Signal(intbv(0)[8:])
     PKTEND = Signal(bool(0))
 

examples/boards/papilio_pro/uart_blinky.py

@@ -26,7 +26,7 @@ def uart_blinky(clock, led, uart_tx, uart_rx):
     For details about the message format see
     /rhea/cores/memmap/command_bridge.py
     """
-    reset = ResetSignal(0, active=0, async=True)
+    reset = ResetSignal(0, active=0, isasync=True)
 
     glbl = Global(clock, reset)
     ledreg = Signal(intbv(0)[8:])

examples/boards/parallella/test_serdes/parallella_serdes.py

@@ -80,7 +80,7 @@ def build(args):
     # @todo: use parallella board, use an ISE support board for now ...
     brd = get_board('parallella')
     # @todo: temporary for existing board
-    # brd.add_reset('reset', active=1, async=True, pins=('N20',))
+    # brd.add_reset('reset', active=1, isasync=True, pins=('N20',))
     brd.add_port_name('serial_tx_p', 'gpio_p', slice(4, 8))
     brd.add_port_name('serial_tx_n', 'gpio_n', slice(4, 8))
     brd.add_port_name('serial_rx_p', 'gpio_p', slice(8, 12))

examples/boards/parallella/test_serdes/test_parallella_serdes.py

@@ -18,7 +18,7 @@ def test_parallella_serdes(args=None):
     args = tb_default_args(args)
 
     clock = Clock(0, frequency=50e6)
-    reset = Reset(0, active=1, async=True)
+    reset = Reset(0, active=1, isasync=True)
     txp = Signal(intbv(0)[6:])
     txn = Signal(intbv(0)[6:])
     rxp = Signal(intbv(0)[6:])

examples/boards/xula/vga/test_xula_vga.py

@@ -22,7 +22,7 @@ def test_xula_vga(args=None):
     color_depth = (3, 4, 3,)
 
     clock = Clock(0, frequency=12e6)
-    reset = Reset(0, active=1, async=False)
+    reset = Reset(0, active=1, isasync=False)
     glbl = Global(clock, reset)
     vga = VGA(color_depth=color_depth)
     vga_hsync, vga_vsync = Signals(bool(0), 2)

examples/boards/xula/vga/xula_vga.py

@@ -38,7 +38,7 @@ def xula_vga(
     """
     # stub out reset if needed
     if reset is None:
-        reset = ResetSignal(0, active=0, async=False)
+        reset = ResetSignal(0, active=0, isasync=False)
 
         @always(clock.posedge)
         def reset_stub():
@@ -75,7 +75,7 @@ def convert(color_depth=(10, 10, 10,)):
     """ convert the vgasys to verilog
     """
     clock = Clock(0, frequency=50e6)
-    reset = Reset(0, active=0, async=False)
+    reset = Reset(0, active=0, isasync=False)
     vselect = Signal(bool(0))
 
     hsync = Signal(bool(0))

examples/boards/xula/xula_blinky_host.py

@@ -70,7 +70,7 @@ def beh_assign():
 def build(args):
     brd = get_board('xula2_stickit_mb')
     brd.add_port_name('led', 'pm2', slice(0, 8))
-    brd.add_reset('reset', active=0, async=True, pins=('H2',))
+    brd.add_reset('reset', active=0, isasync=True, pins=('H2',))
     flow = brd.get_flow(top=xula2_blinky_host)
     flow.run()
     info = flow.get_utilization()

examples/boards/zybo/device_primitives/test.py

@@ -12,7 +12,7 @@
 def test_devprim(args=None):
     args = tb_default_args(args)
     clock = Clock(0, frequency=125e6)
-    reset = Reset(0, active=0, async=True)
+    reset = Reset(0, active=0, isasync=True)
     leds = Signal(intbv(0)[4:])
 
     @myhdl.block

examples/build/blink.py

@@ -30,7 +30,7 @@ def rtl_assign():
             led.next[ii] = 0
 
     if reset is None:
-        reset = ResetSignal(0, active=0, async=False)
+        reset = ResetSignal(0, active=0, isasync=False)
 
         @always(clock.posedge)
         def rtl_reset():

examples/cores/fifo36/ex_fifo36.py

@@ -120,7 +120,7 @@ def convert(args=None):
     dst_rdy_i = Signal(bool(0))
     occupied = Signal(intbv(0)[16:])
 
-    reset = ResetSignal(0, active=1, async=True)
+    reset = ResetSignal(0, active=1, isasync=True)
 
     inst = fifo_2clock_cascade(
         wclk, datain, src_rdy_i, dst_rdy_o, space,

examples/cores/fpgalink/led/fpgalink_led.py

@@ -88,7 +88,7 @@ def convert():
     FLAGA,FLAGB,FLAGC,FLAGD = [Signal(bool(0)) for ii in range(4)]
     ADDR = Signal(intbv(0)[2:])
     IFCLK = Signal(bool(0))
-    RST = ResetSignal(bool(1), active=0, async=True)
+    RST = ResetSignal(bool(1), active=0, isasync=True)
     LEDS = Signal(intbv(0)[8:])
     PKTEND = Signal(bool(0))
 

examples/cores/fpgalink/led/fpgalink_led_tri.py

@@ -106,7 +106,7 @@ def convert():
     FLAGA,FLAGB,FLAGC,FLAGD = [Signal(bool(0)) for ii in range(4)]
     ADDR = Signal(intbv(0)[2:])
     IFCLK = Signal(bool(0))
-    RST = ResetSignal(bool(1), active=0, async=True)
+    RST = ResetSignal(bool(1), active=0, isasync=True)
     leds = Signal(intbv(0)[8:])
     PKTEND = Signal(bool(0))
 

rhea/build/boards/altera/de0cv.py

@@ -26,7 +26,7 @@ class DE0CV(FPGA):
     }
 
     default_resets = {
-        'reset': dict(active=0, async=True, pins=('P22',))
+        'reset': dict(active=0, isasync=True, pins=('P22',))
     }
 
     default_ports = {

rhea/build/boards/altera/de0nano.py

@@ -23,7 +23,7 @@ class DE0Nano(FPGA):
     }
 
     default_resets = {
-        'reset': dict(active=0, async=True, pins=('J15',))
+        'reset': dict(active=0, isasync=True, pins=('J15',))
     }
 
     default_ports = {

rhea/build/boards/altera/de0nano_soc.py

@@ -26,9 +26,9 @@ class DE0NanoSOC(FPGA):
     }
 
     default_resets = {
-        'reset': dict(active=0, async=True, pins=('AH16',))
+        'reset': dict(active=0, isasync=True, pins=('AH16',))
     }
-    
+
     default_ports = {
         'led': dict(pins=('W15', 'AA24', 'V16', 'V15',
                           'AF26', 'AE26', 'Y16', 'AA23',)),

rhea/build/boards/altera/de1_soc.py

@@ -33,9 +33,9 @@ class DE1SOC(FPGA):
     default_resets = {
         # if an external reset is desired push button 0 (key0)
         # can be used.  Note this overlaps with "key[0]"
-        'reset': dict(active=0, async=True, pins=('AA14',))
+        'reset': dict(active=0, isasync=True, pins=('AA14',))
     }
-    
+
     default_ports = {
         'led': dict(pins=('V16', 'W16', 'V17', 'V18', 'W17',
                           'W19', 'Y19', 'W20', 'W21', 'Y21')),

rhea/build/boards/xilinx/_atlys.py

@@ -17,7 +17,7 @@ class Atlys(FPGA):
     }
 
     default_resets = {
-        'reset': dict(active=0, async=True, pins=('T15',)),
+        'reset': dict(active=0, isasync=True, pins=('T15',)),
     }
 
     default_ports = {

rhea/build/boards/xilinx/_mojo.py

@@ -27,7 +27,7 @@ class Mojo(FPGA):
 
     default_resets = {
         # rst_n in documentation
-        'reset': dict(active=0, async=True, pins=(38,),
+        'reset': dict(active=0, isasync=True, pins=(38,),
                       iostandard='LVTTL')
     }
 

rhea/build/boards/xilinx/_sx1.py

@@ -14,11 +14,11 @@ class SX1(FPGA):
     default_clocks = {
         'clock': dict(frequency=48e6, pins=(35,)),
     }
-    
+
     default_resets = {
-        'reset': dict(active=0, async=True, pins=(13,)),    
+        'reset': dict(active=0, isasync=True, pins=(13,)),
     }
-    
+
     default_ports = {
         'led': dict(pins=(90, 91, 92, 94, 95, 96, 99)),
 

rhea/build/boards/xilinx/_ufo400.py

@@ -16,7 +16,7 @@ class UFO400(FPGA):
     }
 
     default_resets = {
-        'reset': dict(active=0, async=True, pins=(8,)),    
+        'reset': dict(active=0, isasync=True, pins=(8,)),
     }
 
     default_ports = {

rhea/build/boards/xilinx/_xupv2p.py

@@ -15,7 +15,7 @@ class XUPV2P(FPGA):
     }
 
     default_resets = {
-        'reset': dict(active=0, async=True, pins=('AH5',)),    
+        'reset': dict(active=0, isasync=True, pins=('AH5',)),
     }
 
     default_ports = {

rhea/build/boards/xilinx/zybo.py

@@ -17,7 +17,7 @@ class Zybo(FPGA):
     }
 
     # default_resets = {
-    #     'reset': dict(active=0, async=True, pins=('G14',),
+    #     'reset': dict(active=0, isasync=True, pins=('G14',),
     #                   iostandard='LVCMOS25'),  #  drive=4
     # }
 

rhea/build/fpga.py

@@ -92,11 +92,11 @@ def add_clock(self, name, frequency=1, pins=None, **pattr):
         self._clocks[name] = p
         self._ports[name] = p
 
-    def add_reset(self, name, active, async, pins, **pattr):
-        assert isinstance(async, bool)
+    def add_reset(self, name, active, isasync, pins, **pattr):
+        assert isinstance(isasync, bool)
         assert active in (0,1,)
-        p = Port(name, pins, 
-                 sigtype=Reset(0, active=active, async=async), **pattr)
+        p = Port(name, pins,
+                 sigtype=Reset(0, active=active, isasync=isasync), **pattr)
         # add to the reset and port dicts
         self._resets[name] = p
         self._ports[name] = p

rhea/cores/fifo/fifo_async.py

@@ -50,8 +50,8 @@ def fifo_async(clock_write, clock_read, fifobus, reset, size=128):
 
     # sync'd resets, the input reset is more than likely sync'd to one
     # of the clock domains, sync both regardless ...
-    wrst = ResetSignal(reset.active, active=reset.active, async=reset.async)
-    rrst = ResetSignal(reset.active, active=reset.active, async=reset.async)
+    wrst = ResetSignal(reset.active, active=reset.active, isasync=reset.isasync)
+    rrst = ResetSignal(reset.active, active=reset.active, isasync=reset.isasync)
 
     # @todo: if ResetSignal use the active attribute to determine 
     #        if 'not reset' or 'reset'.  If the active==0 then 

rhea/cores/fifo/fifo_fast.py

@@ -142,7 +142,7 @@ def beh_occupancy():
 
 # fifo_fast block attributes, these will affect all instances
 fifo_fast.portmap = dict(
-    reset=ResetSignal(0, active=1, async=False),
+    reset=ResetSignal(0, active=1, isasync=False),
     clock=Signal(bool(0)),
     fbus=FIFOBus()
 )

rhea/cores/sdram/sdram_sdr.py

@@ -75,8 +75,8 @@ def rtl_sdram_controller():
 # default portmap
 clock = Clock(0, frequency=100e6)
 sdram_sdr_controller.portmap = {
-    'clock': clock, 
-    'reset': ResetSignal(0, active=0, async=False),
+    'clock': clock,
+    'reset': ResetSignal(0, active=0, isasync=False),
     'ibus': None,
     'extmem': SDRAMInterface(clock)
 }

rhea/cores/usbext/fpgalink/_fl_convert.py

@@ -83,14 +83,14 @@ def hdl():
             chanAddr_out.next = True
             h2fData_out.next = 3
             h2fValid_out.next = True
-            f2hReady_out.next = True            
+            f2hReady_out.next = True
 
     return hdl
 
 
 def convert(dir=None):
     clk_in = Signal(bool(0))
-    reset_in = ResetSignal(bool(0), active=0, async=True)
+    reset_in = ResetSignal(bool(0), active=0, isasync=True)
     fx2FifoSel_out = Signal(bool(0))
     #fxData_io
     fx2Data_in = Signal(intbv(0)[8:])

rhea/cores/usbext/fpgalink/fpgalink_fx2.py

@@ -13,7 +13,7 @@ def get_interfaces():
     """ Single function to get the buses
     """
     clock = Signal(bool(1))
-    reset = ResetSignal(bool(1), active=0, async=False)
+    reset = ResetSignal(bool(1), active=0, isasync=False)
 
     # Get an object that can be used for the "interfaces"
     fx2bus = Bus()  # External to the FPGA

rhea/models/usbext/fx2/fx2_model.py

@@ -139,7 +139,7 @@ def get_bus(self):
         fx2 = Bus()
         fx2.IFCLK = Signal(bool(1))
         (fx2.SLWR, fx2.SLRD, fx2.SLOE) = [Signal(bool(dbl)) for _ in range(3)]
-        fx2.RST = ResetSignal(bool(1), active=0, async=True)
+        fx2.RST = ResetSignal(bool(1), active=0, isasync=True)
         fx2.ADDR = Signal(intbv(0)[2:])
         fx2.FDI, fx2.FDO = [Signal(intbv(0)[8:]) for _ in (1, 2)]
         (fx2.FLAGA, fx2.FLAGB,

rhea/system/glbl.py

@@ -22,7 +22,7 @@ def __init__(self, clock=None, reset=None, frequency=1):
             self.clock = clock
 
         if reset is None:            
-            self.reset = Reset(0, active=1, async=False) 
+            self.reset = Reset(0, active=1, isasync=False)
         else:
             self.reset = reset
 

rhea/system/memmap/avalonmm.py

@@ -34,7 +34,7 @@ def __init__(self, glbl=None, data_width=8, address_width=16, name=None):
             self.clk = glbl.clock
 
         if glbl.reset is None:
-            self.reset = Reset(0, active=1, async=False)
+            self.reset = Reset(0, active=1, isasync=False)
         else:
             self.reset = glbl.reset