This repository contains an implementation of FPGA netlist timing delay calculations using parallel patterns in the NVIDIA Thrust library. The delay model is inspired by the cost model used in the timing-driven simulated annealing placement method in the VPR, which is now part of the popular FPGA CAD suite, VTR (published here).
The parallel method described here algorithm was designed and developed as part of Christian Fobel's PhD research in the School of Computer Science at the University of Guelph in Guelph, Ontario, Canada, with funding support from NSERC.
The source code in this project is licensed as described in the contained
COPYING file.
Copyright (c) 2015 Christian Fobel