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WebAssembly SIMD support in Chakra #4200

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merged 72 commits into from Dec 12, 2017
Merged

WebAssembly SIMD support in Chakra #4200

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2ea6c86
Adding WASM-SIMD feature flag
arunetm Feb 6, 2017
79c541b
arithmetics tests
Krovatkin Mar 10, 2017
e87d84f
fixes after Mike's changes to writers to handle unreachable code veri…
Krovatkin Mar 23, 2017
6bbabaf
CI failures
Krovatkin Mar 23, 2017
6b89b85
CI fixes 2
Krovatkin Mar 23, 2017
1e30eec
CI 3 fixing win7 failures
Krovatkin Mar 24, 2017
65f235c
llvm fixes 2
Krovatkin Mar 29, 2017
952760c
constantsize the magic number representing the max num of lanes
Krovatkin Mar 30, 2017
5564041
initial switch to m128
Krovatkin Mar 30, 2017
501145b
addressing mike's feedback
Krovatkin Mar 30, 2017
347d683
mike's feedback p2
Krovatkin Apr 3, 2017
e373f82
linking errors on osx/static
Krovatkin Apr 4, 2017
5e21fbd
[MERGE #2736 @Krovatkin] Initial PR for Wasm.Simd. Includes build/ext…
Cellule Apr 5, 2017
38ec30d
fix uint16_t bbrk
Krovatkin Apr 6, 2017
37a8368
[MERGE #2791 @Krovatkin] fix uint16_t bbrk on wasm.simd branch
Cellule Apr 11, 2017
5ceb609
new binary format + extractLane
Krovatkin Jun 15, 2017
3d31f23
working loads and stores needs clean up
Krovatkin Apr 28, 2017
a6fed1a
simd const operators
Krovatkin Jun 2, 2017
6c0f096
[MERGE #3185 @Krovatkin] wasm.simd new binary format + load/store + …
Cellule Jun 27, 2017
8798239
replaceLane + tests
Krovatkin May 25, 2017
e7f738c
[MERGE #3237 @Krovatkin] Wasm.simd Negation, Splat, ReplaceLane + tests
Cellule Jun 30, 2017
7650717
simd convert and truncate instrs + tests
Krovatkin Jun 1, 2017
b43c0ce
logical ops
Krovatkin May 31, 2017
8d5ea33
reduction ops fix for non-canonical bool values
Krovatkin Jul 6, 2017
cff6be7
interpreter fix for non-canonical bool values
Krovatkin Jul 7, 2017
e1ab43b
[MERGE #3288 @Krovatkin] Logical & TruncConv Ops + Tests
Cellule Jul 13, 2017
e4acc19
Use appropiate overloads (matching lane width) of CanonicalizeToBools
Krovatkin Jul 13, 2017
52e6330
[MERGE #3342 @Krovatkin] WASM.SIMD Use appropriate overloads (matchin…
Cellule Jul 13, 2017
3d2fbc9
comparison ops
Krovatkin Apr 12, 2017
00a1a3c
binary ops + tests
Krovatkin Jul 14, 2017
bc130b8
merge
Krovatkin Jul 20, 2017
95e565b
[MERGE #3348 @Krovatkin] WASM.SIMD Comparison ops for 32x4 types
Cellule Jul 24, 2017
3975f88
flag/macro fix
Krovatkin Jul 25, 2017
9f6ceb0
more bbrk fixes
Krovatkin Jul 25, 2017
9e4cc60
missing thunk clang/x64
Krovatkin Jul 25, 2017
e5018e8
prettier macros
Krovatkin Jul 26, 2017
d5e5646
ENABLE_WASM TO ENABLE_WASM_SIMD
Krovatkin Jul 26, 2017
4e0a014
Merge remote-tracking branch 'msft/master' into wasm.simd.merge
Krovatkin Jul 26, 2017
074bc4e
removing redundant exclude_xplat tags & resolving code conflict
Krovatkin Jul 27, 2017
7c7fe6c
fixes out-of-jit crash while accessing a scratch storage of threadcon…
Krovatkin Aug 2, 2017
35be042
Merge branch 'wasm.simd.merge' into build/micfer/wasm.simd.merge
Cellule Aug 3, 2017
12c53f9
[master>wasm.simd] Integrate master to wasm.simd
Cellule Aug 3, 2017
25d29a0
int64x2 infra
Krovatkin Aug 1, 2017
b8c4da2
removing unused code
Krovatkin Aug 11, 2017
12c4409
clean up, add asserts to Extract/Replace, simplify tests
Krovatkin Aug 17, 2017
8c98360
add some comments & todos, fix add a header to a project group
Krovatkin Aug 18, 2017
dc8893b
[MERGE #3490 @Krovatkin] WASM.SIMD int64x2 operations
arunetm-zz Sep 15, 2017
bf8d8e7
Merge remote-tracking branch 'msft/master' into wasm.simd
Krovatkin Sep 15, 2017
8ca37c4
Merge branch 'master' into wasm.simd
Cellule Sep 18, 2017
7c3ca9c
bitselect
Krovatkin Aug 16, 2017
4a7149b
refactor & cleanup for bitselect & shuffle
Krovatkin Sep 25, 2017
287b00f
use Wasm::Simd::MAX_LANES consistently
Krovatkin Sep 25, 2017
a97eaee
move AsmReg19 back to AsmJsByteCodeWriter
Krovatkin Sep 25, 2017
b1761af
move a call to checkbytes before reading indices remove inline
Krovatkin Sep 25, 2017
becd54a
float64x2
Krovatkin Sep 8, 2017
7d24685
[MERGE #3763 @Krovatkin] WASM.SIMD BitSelect & Shuffle ops + Tests
MikeHolman Sep 26, 2017
5587cb4
formatting fixes
Krovatkin Sep 26, 2017
8d04ab3
simplify Lowerer seq for Simd128_ReplaceLane_D2
Krovatkin Sep 27, 2017
d4d65f0
add assert in SIMD128InnerReplaceLaneD2
Krovatkin Sep 27, 2017
89d45e5
[MERGE #3807 @Krovatkin] WASM.SIMD Float64x2 Ops
Cellule Oct 4, 2017
647fc62
Merge from Master to wasm.simd
arunetm-zz Oct 20, 2017
37e52c1
Fixing x86 build failures
arunetm-zz Oct 20, 2017
66bb1a9
Merge remote-tracking branch 'origin/master' into build/arunetm/wasm.…
arunetm-zz Oct 20, 2017
d3c6d41
Addressing WASM.SIMD xplat failure.
arunetm-zz Oct 26, 2017
e12dac3
truncation & conversion ops for 64x2 types
Krovatkin Sep 12, 2017
f70f51c
[MERGE #4074 @arunetm] WASM.SIMD: Trunc & Conv ops for 64x2 types
arunetm-zz Oct 30, 2017
7c94e25
Merge branch 'master' into build/arunetm/wasm.simd-merge
arunetm Nov 9, 2017
eebff83
Merge branch 'master' into wasm.simd
arunetm-zz Nov 22, 2017
1f295d2
Incorporating CR feedback1
arunetm Nov 26, 2017
0291cc2
Code review 2
arunetm Dec 7, 2017
6bf5bbc
Merge branch 'master' into pr/arunetm/wasm.simd
arunetm-zz Dec 9, 2017
982f59e
Merge branch 'master' into pr/arunetm/wasm.simd
arunetm-zz Dec 10, 2017
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309 changes: 266 additions & 43 deletions lib/Backend/IRBuilderAsmJs.cpp
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5 changes: 3 additions & 2 deletions lib/Backend/IRBuilderAsmJs.h
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Expand Up @@ -180,7 +180,7 @@ class IRBuilderAsmJs
#include "ByteCode/LayoutTypesAsmJs.h"
void BuildSimd_1Ints(Js::OpCodeAsmJs newOpcode, uint32 offset, IRType dstSimdType, Js::RegSlot* srcRegSlots, Js::RegSlot dstRegSlot, uint LANES);
void BuildSimd_1Int1(Js::OpCodeAsmJs newOpcode, uint32 offset, Js::RegSlot dstRegSlot, Js::RegSlot src1RegSlot, IRType simdType);
void BuildSimd_2Int2(Js::OpCodeAsmJs newOpcode, uint32 offset, Js::RegSlot dstRegSlot, Js::RegSlot src1RegSlot, Js::RegSlot src2RegSlot, Js::RegSlot src3RegSlot, IRType simdType);
void BuildSimd_2Int2(Js::OpCodeAsmJs newOpcode, uint32 offset, Js::RegSlot dstRegSlot, Js::RegSlot src1RegSlot, Js::RegSlot src2RegSlot, Js::RegSlot src3RegSlot, IRType simdType, IRType valType = TyInt32);
void BuildSimd_2(Js::OpCodeAsmJs newOpcode, uint32 offset, Js::RegSlot dstRegSlot, Js::RegSlot src1RegSlot, IRType simdType);
void BuildSimd_2Int1(Js::OpCodeAsmJs newOpcode, uint32 offset, Js::RegSlot dstRegSlot, Js::RegSlot src1RegSlot, Js::RegSlot src2RegSlot, IRType simdType);
void BuildSimd_3(Js::OpCodeAsmJs newOpcode, uint32 offset, Js::RegSlot dstRegSlot, Js::RegSlot src1RegSlot, Js::RegSlot src2RegSlot, IRType simdType);
Expand All @@ -193,7 +193,7 @@ class IRBuilderAsmJs
void BuildWasmLoopStart(Js::OpCodeAsmJs newOpcode, uint offset);
void BuildWasmMemAccess(Js::OpCodeAsmJs newOpcode, uint32 offset, uint32 slotIndex, Js::RegSlot value, uint32 constOffset, Js::ArrayBufferView::ViewType viewType);
void BuildAsmTypedArr(Js::OpCodeAsmJs newOpcode, uint32 offset, uint32 slotIndex, Js::RegSlot value, Js::ArrayBufferView::ViewType viewType);
void BuildAsmSimdTypedArr(Js::OpCodeAsmJs newOpcode, uint32 offset, uint32 slotIndex, Js::RegSlot value, Js::ArrayBufferView::ViewType viewType, uint8 DataWidth);
void BuildAsmSimdTypedArr(Js::OpCodeAsmJs newOpcode, uint32 offset, uint32 slotIndex, Js::RegSlot value, Js::ArrayBufferView::ViewType viewType, uint8 DataWidth, uint32 simdOffset);
void BuildAsmCall(Js::OpCodeAsmJs newOpcode, uint32 offset, Js::ArgSlot argCount, Js::RegSlot ret, Js::RegSlot function, int8 returnType, Js::ProfileId profileId);
void BuildAsmReg1(Js::OpCodeAsmJs newOpcode, uint32 offset, Js::RegSlot dstReg);
void BuildBrInt1(Js::OpCodeAsmJs newOpcode, uint32 offset, int32 relativeOffset, Js::RegSlot src);
Expand Down Expand Up @@ -266,6 +266,7 @@ class IRBuilderAsmJs
#define Bool32x4_Type Js::RegSlot
#define Int32x4_Type Js::RegSlot
#define Float64x2_Type Js::RegSlot
#define Int64x2_Type Js::RegSlot
#define Int16x8_Type Js::RegSlot
#define Bool16x8_Type Js::RegSlot
#define Int8x16_Type Js::RegSlot
Expand Down
1 change: 1 addition & 0 deletions lib/Backend/IRTypeList.h
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Expand Up @@ -32,6 +32,7 @@ IRTYPE(Simd128U16, Simd, 16, b(16), 1, simd128)
IRTYPE(Simd128B4, Simd, 16, b(16), 1, simd128)
IRTYPE(Simd128B8, Simd, 16, b(16), 1, simd128)
IRTYPE(Simd128B16, Simd, 16, b(16), 1, simd128)
IRTYPE(Simd128I2, Simd, 16, b(16), 1, simd128)
IRTYPE(Simd128D2, Simd, 16, b(16), 1, simd128) // SIMD end


Expand Down
12 changes: 12 additions & 0 deletions lib/Backend/JnHelperMethodList.h
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Expand Up @@ -347,6 +347,18 @@ HELPERCALL(AllocUninitializedNumber, Js::JavascriptOperators::AllocUninitialized
// SIMD_JS
HELPERCALL(AllocUninitializedSimdF4, Js::JavascriptSIMDFloat32x4::AllocUninitialized, 0)
HELPERCALL(AllocUninitializedSimdI4, Js::JavascriptSIMDInt32x4::AllocUninitialized, 0)

#endif

#ifdef ENABLE_WASM_SIMD
HELPERCALL(Simd128ShRtByScalarU2, Js::SIMDInt64x2Operation::OpShiftRightByScalarU, 0)
HELPERCALL(Simd128ShRtByScalarI2, Js::SIMDInt64x2Operation::OpShiftRightByScalar, 0)
HELPERCALL(Simd128ShLtByScalarI2, Js::SIMDInt64x2Operation::OpShiftLeftByScalar, 0)
HELPERCALL(Simd128ReplaceLaneI2, Js::SIMDInt64x2Operation::OpReplaceLane, 0)
HELPERCALL(Simd128TruncateI2, (void(*)(SIMDValue*, SIMDValue*))&Js::SIMDInt64x2Operation::OpTrunc<int64>, AttrCanThrow)
HELPERCALL(Simd128TruncateU2, (void(*)(SIMDValue*, SIMDValue*))&Js::SIMDInt64x2Operation::OpTrunc<uint64>, AttrCanThrow)
HELPERCALL(Simd128ConvertSD2, (void(*)(SIMDValue*, SIMDValue*))&Js::SIMDFloat64x2Operation::OpConv<int64>, 0)
HELPERCALL(Simd128ConvertUD2, (void(*)(SIMDValue*, SIMDValue*))&Js::SIMDFloat64x2Operation::OpConv<uint64>, 0)
#endif

HELPERCALL(Op_TryCatch, nullptr, 0)
Expand Down
1 change: 1 addition & 0 deletions lib/Backend/Lifetime.h
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Expand Up @@ -14,6 +14,7 @@ class Lifetime
useList(alloc), lastUseLabel(NULL), region(NULL), isSpilled(false), useCount(0), useCountAdjust(0), allDefsCost(0), isLiveAcrossCalls(false),
isLiveAcrossUserCalls(false), isDeadStore(true), isOpHelperSpilled(false), cantOpHelperSpill(false), isOpHelperSpillAsArg(false),
isFloat(0), cantSpill(false), dontAllocate(false), isSecondChanceAllocated(false), isCheapSpill(false), spillStackSlot(NULL),

totalOpHelperLengthByEnd(0), needsStoreCompensation(false), alloc(alloc), regionUseCount(NULL), regionUseCountAdjust(NULL),
cantStackPack(false)
{
Expand Down
2 changes: 1 addition & 1 deletion lib/Backend/Lower.cpp
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Expand Up @@ -3019,7 +3019,7 @@ Lowerer::LowerRange(IR::Instr *instrStart, IR::Instr *instrEnd, bool defaultDoFa
#endif //ENABLE_WASM

default:
#ifdef ENABLE_SIMDJS
#if defined(ENABLE_SIMDJS) || defined(ENABLE_WASM_SIMD)
#if defined(_M_IX86) || defined(_M_X64)
if (IsSimd128Opcode(instr->m_opcode))
{
Expand Down
9 changes: 8 additions & 1 deletion lib/Backend/LowerMDShared.cpp
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Expand Up @@ -504,7 +504,7 @@ LowererMD::Init(Lowerer *lowerer)
{
m_lowerer = lowerer;
this->lowererMDArch.Init(this);
#ifdef ENABLE_SIMDJS
#if defined(ENABLE_SIMDJS) || defined(ENABLE_WASM_SIMD)
Simd128InitOpcodeMap();
#endif
}
Expand Down Expand Up @@ -858,6 +858,9 @@ LowererMD::LowerRet(IR::Instr * retInstr)
case Js::AsmJsRetType::Float64x2:
regType = TySimd128D2;
break;
case Js::AsmJsRetType::Int64x2:
regType = TySimd128I2;
break;
case Js::AsmJsRetType::Int16x8:
regType = TySimd128I8;
break;
Expand Down Expand Up @@ -1721,6 +1724,7 @@ LowererMD::Legalize(IR::Instr *const instr, bool fPostRegAlloc)
case Js::OpCode::PADDB:
case Js::OpCode::PADDSB:
case Js::OpCode::PADDD:
case Js::OpCode::PADDQ:
case Js::OpCode::PADDW:
case Js::OpCode::PADDSW:
case Js::OpCode::PADDUSB:
Expand All @@ -1743,6 +1747,7 @@ LowererMD::Legalize(IR::Instr *const instr, bool fPostRegAlloc)
case Js::OpCode::PSUBB:
case Js::OpCode::PSUBSB:
case Js::OpCode::PSUBD:
case Js::OpCode::PSUBQ:
case Js::OpCode::PSUBW:
case Js::OpCode::PSUBSW:
case Js::OpCode::PSUBUSB:
Expand Down Expand Up @@ -1833,10 +1838,12 @@ LowererMD::Legalize(IR::Instr *const instr, bool fPostRegAlloc)
case Js::OpCode::PSLLDQ:
case Js::OpCode::PSRLW:
case Js::OpCode::PSRLD:
case Js::OpCode::PSRLQ:
case Js::OpCode::PSRAW:
case Js::OpCode::PSRAD:
case Js::OpCode::PSLLW:
case Js::OpCode::PSLLD:
case Js::OpCode::PSLLQ:

Assert(AutoSystemInfo::Data.SSE2Available());
MakeDstEquSrc1<verify>(instr);
Expand Down
34 changes: 24 additions & 10 deletions lib/Backend/LowerMDShared.h
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Expand Up @@ -262,6 +262,7 @@ class LowererMD
IR::Instr * LowerCallI(IR::Instr * callInstr, ushort callFlags, bool isHelper = false, IR::Instr * insertBeforeInstrForCFG = nullptr);
IR::Instr * LoadInt64HelperArgument(IR::Instr * instr, IR::Opnd* opnd);
IR::Instr * LoadHelperArgument(IR::Instr * instr, IR::Opnd * opndArg);
IR::MemRefOpnd * LoadSimdHelperArgument(IR::Instr * instr, uint8 index);
IR::Instr * LoadDoubleHelperArgument(IR::Instr * instr, IR::Opnd * opndArg);
IR::Instr * LoadFloatHelperArgument(IR::Instr * instr, IR::Opnd * opndArg);
IR::Instr * LowerEntryInstr(IR::EntryInstr * entryInstr);
Expand Down Expand Up @@ -318,24 +319,36 @@ class LowererMD
static IR::Instr * InsertCmovCC(const Js::OpCode opCode, IR::Opnd * dst, IR::Opnd* src1, IR::Instr* insertBeforeInstr, bool postRegAlloc = false);

#ifdef ENABLE_SIMDJS
IR::Instr* Simd128LowerConstructor_2(IR::Instr *instr);
IR::Instr* Simd128LowerConstructor_4(IR::Instr *instr);
IR::Instr* Simd128LowerConstructor_8(IR::Instr *instr);
IR::Instr* Simd128LowerConstructor_16(IR::Instr *instr);
IR::Instr* Simd128LowerRcp(IR::Instr *instr, bool removeInstr = true);
IR::Instr* Simd128LowerRcpSqrt(IR::Instr *instr);
IR::Instr* Simd128LowerRcpSqrt(IR::Instr *instr);
void GenerateCheckedSimdLoad(IR::Instr * instr);
void GenerateSimdStore(IR::Instr * instr);
IR::Instr* Simd128LowerSelect(IR::Instr *instr);
#endif

#if defined(ENABLE_SIMDJS) || defined(ENABLE_WASM_SIMD)
void Simd128InitOpcodeMap();
IR::Instr* Simd128Instruction(IR::Instr* instr);
IR::Instr* Simd128LoadConst(IR::Instr* instr);
IR::Instr* LowerSimd128BitSelect(IR::Instr* instr);
bool Simd128TryLowerMappedInstruction(IR::Instr *instr);
IR::Instr* Simd128LowerUnMappedInstruction(IR::Instr *instr);
IR::Instr* Simd128LowerConstructor_2(IR::Instr *instr);
IR::Instr* Simd128LowerConstructor_4(IR::Instr *instr);
IR::Instr* Simd128LowerConstructor_8(IR::Instr *instr);
IR::Instr* Simd128LowerConstructor_16(IR::Instr *instr);
IR::Instr* Simd128LowerLdLane(IR::Instr *instr);
IR::Instr* SIMD128LowerReplaceLane_2(IR::Instr *instr);
void EmitExtractInt64(IR::Opnd* dst, IR::Opnd* src, uint index, IR::Instr *instr);
void EmitInsertInt64(IR::Opnd* dst, uint index, IR::Instr *instr);
void EmitShiftByScalarI2(IR::Instr *instr, IR::JnHelperMethod helper);
IR::Instr* EmitSimdConversion(IR::Instr *instr, IR::JnHelperMethod helper);
IR::Instr* SIMD128LowerReplaceLane_4(IR::Instr *instr);
IR::Instr* SIMD128LowerReplaceLane_8(IR::Instr *instr);
IR::Instr* SIMD128LowerReplaceLane_16(IR::Instr *instr);
IR::Instr* Simd128LowerSplat(IR::Instr *instr);
IR::Instr* Simd128LowerRcp(IR::Instr *instr, bool removeInstr = true);
IR::Instr* Simd128LowerSqrt(IR::Instr *instr);
IR::Instr* Simd128LowerRcpSqrt(IR::Instr *instr);
IR::Instr* Simd128LowerSelect(IR::Instr *instr);
IR::Instr* Simd128LowerNeg(IR::Instr *instr);
IR::Instr* Simd128LowerMulI4(IR::Instr *instr);
IR::Instr* Simd128LowerShift(IR::Instr *instr);
Expand All @@ -359,15 +372,16 @@ class LowererMD
IR::Instr* Simd128LowerLessThanOrEqual(IR::Instr* instr);
IR::Instr* Simd128LowerGreaterThanOrEqual(IR::Instr* instr);
IR::Instr* Simd128LowerMinMax_F4(IR::Instr* instr);
IR::Instr* Simd128LowerMinMaxNum(IR::Instr* instr);
IR::Instr* Simd128LowerAnyTrue(IR::Instr* instr);
IR::Instr* Simd128LowerAllTrue(IR::Instr* instr);
#ifdef ENABLE_WASM_SIMD
IR::Opnd* Simd128CanonicalizeToBoolsBeforeReduction(IR::Instr* instr);
#endif
BYTE Simd128GetTypedArrBytesPerElem(ValueType arrType);
IR::Instr* Simd128CanonicalizeToBools(IR::Instr* instr, const Js::OpCode& cmpOpcode, IR::Opnd& dstOpnd);
IR::Opnd* EnregisterIntConst(IR::Instr* instr, IR::Opnd *constOpnd, IRType type = TyInt32);
IR::Opnd* EnregisterBoolConst(IR::Instr* instr, IR::Opnd *opnd, IRType type);
SList<IR::Opnd*> * Simd128GetExtendedArgs(IR::Instr *instr);
void GenerateCheckedSimdLoad(IR::Instr * instr);
void GenerateSimdStore(IR::Instr * instr);
void CheckShuffleLanes_4(uint8 lanes[], uint8 lanesSrc[], uint *fromSrc1, uint *fromSrc2);
void InsertShufps(uint8 lanes[], IR::Opnd *dst, IR::Opnd *src1, IR::Opnd *src2, IR::Instr *insertBeforeInstr);
#endif
Expand Down