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eh2_dec_decode_ctl.sv
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eh2_dec_decode_ctl.sv
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// SPDX-License-Identifier: Apache-2.0
// Copyright 2020 Western Digital Corporation or its affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
module eh2_dec_decode_ctl
import eh2_pkg::*;
#(
`include "eh2_param.vh"
)
(
input logic [pt.NUM_THREADS-1:0] active_thread_l2clk,
input dec_i0_debug_valid_d,
input dec_i1_debug_valid_d,
input logic dec_i0_csr_global_d,
input eh2_predecode_pkt_t dec_i0_predecode,
input eh2_predecode_pkt_t dec_i1_predecode,
input logic [pt.NUM_THREADS-1:0] dec_tlu_force_halt, // invalidate nonblock load cam on a force halt event
input logic [pt.NUM_THREADS-1:0] dec_tlu_debug_stall, // stall decode while waiting on core to empty
input logic [pt.NUM_THREADS-1:0] dec_tlu_flush_extint,
input logic dec_i0_tid_d,
input logic dec_i1_tid_d,
output logic dec_i0_pc4_e4,
output logic dec_i1_pc4_e4,
output logic dec_i0_debug_valid_wb,
output logic dec_i0_secondary_d, // for power
output logic dec_i0_secondary_e1,
output logic dec_i0_secondary_e2,
output logic dec_i1_secondary_d,
output logic dec_i1_secondary_e1,
output logic dec_i1_secondary_e2,
output logic dec_i0_branch_d,
output logic dec_i0_branch_e1,
output logic dec_i0_branch_e2,
output logic dec_i0_branch_e3,
output logic dec_i1_branch_d,
output logic dec_i1_branch_e1,
output logic dec_i1_branch_e2,
output logic dec_i1_branch_e3,
output logic dec_div_cancel, // cancel divide operation
output logic dec_extint_stall,
input logic [15:0] dec_i0_cinst_d, // 16b compressed instruction
input logic [15:0] dec_i1_cinst_d,
output logic [31:0] dec_i0_inst_wb1, // 32b instruction at wb+1 for trace encoder
output logic [31:0] dec_i1_inst_wb1,
output logic [31:1] dec_i0_pc_wb1, // 31b pc at wb+1 for trace encoder
output logic [31:1] dec_i1_pc_wb1,
output logic [pt.NUM_THREADS-1:0] dec_i1_cancel_e1,
input logic [31:0] lsu_rs1_dc1,
input logic lsu_nonblock_load_valid_dc1, // valid nonblock load at dc3
input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_dc1, // -> corresponding tag
input logic lsu_nonblock_load_inv_dc2, // invalidate request for nonblock load dc2
input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_dc2, // -> corresponding tag
input logic lsu_nonblock_load_inv_dc5, // invalidate request for nonblock load dc5
input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_dc5, // -> corresponding tag
input logic lsu_nonblock_load_data_valid, // valid nonblock load data back
input logic lsu_nonblock_load_data_error, // nonblock load bus error
input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // -> corresponding tag
input logic lsu_nonblock_load_data_tid,
input logic [31:0] lsu_nonblock_load_data, // nonblock load data
input logic [3:0] dec_i0_trigger_match_d, // i0 decode trigger matches
input logic [3:0] dec_i1_trigger_match_d, // i1 decode trigger matches
input logic [pt.NUM_THREADS-1:0] dec_tlu_wr_pause_wb, // pause instruction at wb
input logic dec_tlu_pipelining_disable, // pipeline disable - presync, i0 decode only
input logic dec_tlu_dual_issue_disable, // i0 decode only
input logic dec_tlu_trace_disable, // trace disable
input logic [3:0] lsu_trigger_match_dc4, // lsu trigger matches
input logic[pt.NUM_THREADS-1:0] lsu_pmu_misaligned_dc3, // perf mon: load/store misalign
input logic [pt.NUM_THREADS-1:0] dec_tlu_flush_leak_one_wb, // leak1 instruction
input logic dec_debug_fence_d, // debug fence instruction
input logic [1:0] dbg_cmd_wrdata, // disambiguate fence, fence_i
input logic dec_i0_icaf_d, // icache access fault
input logic dec_i1_icaf_d,
input logic dec_i0_icaf_second_d, // i0 instruction access fault at decode for second 2B of 4B inst
input logic [1:0] dec_i0_icaf_type_d, // i0 instruction access fault type
input logic dec_i0_dbecc_d, // icache/iccm double-bit error
input logic dec_i1_dbecc_d,
input eh2_br_pkt_t dec_i0_brp, // branch packet
input eh2_br_pkt_t dec_i1_brp,
input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index, // i0 branch index
input logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr, // BP FGHR
input logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag, // BP tag
input logic [pt.BTB_TOFFSET_SIZE-1:0] dec_i0_bp_toffset, // BP tag
input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i1_bp_index, // i0 branch index
input logic [pt.BHT_GHR_SIZE-1:0] dec_i1_bp_fghr, // BP FGHR
input logic [pt.BTB_BTAG_SIZE-1:0] dec_i1_bp_btag, // BP tag
input logic [pt.BTB_TOFFSET_SIZE-1:0] dec_i1_bp_toffset, // BP tag
input logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index, // Fully associt btb index (only care about i0 for errors)
input logic [pt.NUM_THREADS-1:0] lsu_idle_any, // lsu idle: if fence instr & ~lsu_idle then stall decode
input logic [pt.NUM_THREADS-1:0] lsu_load_stall_any, // stall any load at decode
input logic [pt.NUM_THREADS-1:0] lsu_store_stall_any, // stall any store at decode
input logic [pt.NUM_THREADS-1:0] lsu_amo_stall_any, // This is for blocking amo
input logic dma_dccm_stall_any, // stall any load/store at decode
input logic exu_div_wren, // div finish this cycle
input logic dec_tlu_i0_kill_writeb_wb, // I0 is flushed, don't writeback any results to arch state
input logic dec_tlu_i1_kill_writeb_wb, // I1 is flushed, don't writeback any results to arch state
input logic [pt.NUM_THREADS-1:0] dec_tlu_flush_lower_wb, // trap lower flush
input logic [pt.NUM_THREADS-1:0] dec_tlu_flush_pause_wb, // don't clear pause state on initial lower flush
input logic [pt.NUM_THREADS-1:0] dec_tlu_presync_d, // CSR read needs to be presync'd
input logic [pt.NUM_THREADS-1:0] dec_tlu_postsync_d, // CSR ops that need to be postsync'd
input logic [31:0] exu_mul_result_e3, // multiply result
input logic dec_i0_pc4_d, // inst is 4B inst else 2B
input logic dec_i1_pc4_d,
input logic [31:0] lsu_result_dc3, // load result
input logic [31:0] lsu_result_corr_dc4, // load result - corrected data for writing gprs; not for bypassing
input logic lsu_sc_success_dc5, // store conditional matched ( 1 = success, which means the GPR should write 0 )
input logic [pt.NUM_THREADS-1:0] exu_i0_flush_final, // lower flush or i0 flush at e2
input logic [pt.NUM_THREADS-1:0] exu_i1_flush_final, // lower flush or i1 flush at e2
input logic [31:1] exu_i0_pc_e1, // pcs at e1
input logic [31:1] exu_i1_pc_e1,
input logic [31:0] dec_i0_instr_d, // inst at decode
input logic [31:0] dec_i1_instr_d,
input logic dec_ib0_valid_d, // inst valid at decode
input logic dec_ib1_valid_d,
input logic [31:0] exu_i0_result_e1, // from primary alu's
input logic [31:0] exu_i1_result_e1,
input logic [31:0] exu_i0_result_e4, // from secondary alu's
input logic [31:0] exu_i1_result_e4,
input logic clk, // for rvdffe's
input logic active_clk,
input logic free_l2clk,
input logic clk_override, // test stuff
input logic rst_l,
output logic dec_i0_rs1_en_d, // rs1 enable at decode
output logic dec_i0_rs2_en_d,
output logic [4:0] dec_i0_rs1_d, // rs1 logical source
output logic [4:0] dec_i0_rs2_d,
output logic dec_i0_tid_e4, // needed to maintain RS in BP
output logic dec_i1_tid_e4,
output logic [31:0] dec_i0_immed_d, // 32b immediate data decode
output logic dec_i1_rs1_en_d,
output logic dec_i1_rs2_en_d,
output logic [4:0] dec_i1_rs1_d,
output logic [4:0] dec_i1_rs2_d,
output logic [31:0] dec_i1_immed_d,
output logic [pt.BTB_TOFFSET_SIZE:1] dec_i0_br_immed_d, // 12b branch immediate
output logic [pt.BTB_TOFFSET_SIZE:1] dec_i1_br_immed_d,
output eh2_alu_pkt_t i0_ap, // alu packets
output eh2_alu_pkt_t i1_ap,
output logic dec_i0_decode_d, // i0 decode
output logic dec_i1_decode_d,
output logic dec_i0_alu_decode_d, // decode to primary alu's
output logic dec_i1_alu_decode_d,
output logic [31:0] i0_rs1_bypass_data_d, // i0 rs1 bypass data
output logic [31:0] i0_rs2_bypass_data_d, // i0 rs2 bypass data
output logic [31:0] i1_rs1_bypass_data_d,
output logic [31:0] i1_rs2_bypass_data_d,
output logic [4:0] dec_i0_waddr_wb, // i0 logical source to write to gpr's
output logic dec_i0_wen_wb, // i0 write enable
output logic dec_i0_tid_wb, // i0 write tid
output logic [31:0] dec_i0_wdata_wb, // i0 write data
output logic [4:0] dec_i1_waddr_wb,
output logic dec_i1_wen_wb,
output logic dec_i1_tid_wb,
output logic [31:0] dec_i1_wdata_wb,
output logic dec_i0_select_pc_d, // i0 select pc for rs1 - branches
output logic dec_i1_select_pc_d,
output logic dec_i0_rs1_bypass_en_d, // i0 rs1 bypass enable
output logic dec_i0_rs2_bypass_en_d, // i0 rs2 bypass enable
output logic dec_i1_rs1_bypass_en_d,
output logic dec_i1_rs2_bypass_en_d,
output eh2_lsu_pkt_t lsu_p, // load/store packet
output eh2_mul_pkt_t mul_p, // multiply packet
output eh2_div_pkt_t div_p, // divide packet
output logic div_tid_wb, // DIV write tid to GPR
output logic [4:0] div_waddr_wb, // DIV write address to GPR
output logic [11:0] dec_lsu_offset_d,
output logic dec_i0_lsu_d, // chose which gpr value to use
output logic dec_i1_lsu_d,
output logic dec_i0_mul_d, // chose which gpr value to use
output logic dec_i1_mul_d,
output logic dec_i0_div_d, // chose which gpr value to use
output logic [pt.NUM_THREADS-1:0] flush_final_e3, // flush final at e3: i0 or i1
output logic [pt.NUM_THREADS-1:0] i0_flush_final_e3, // i0 flush final at e3
// CSR interface
input logic [31:0] dec_i0_csr_rddata_d, // csr read data at wb
input logic dec_i0_csr_legal_d, // csr indicates legal operation
input logic [31:0] exu_i0_csr_rs1_e1, // rs1 for csr instr
output logic dec_i0_csr_ren_d, // valid csr decode
output logic dec_i0_csr_wen_unq_d, // valid csr with write - for csr legal
output logic dec_i0_csr_any_unq_d, // valid csr - for csr legal
output logic dec_i0_csr_wen_wb, // csr write enable at wb
output logic [11:0] dec_i0_csr_rdaddr_d, // read address for csr
output logic [11:0] dec_i0_csr_wraddr_wb, // write address for csr
output logic [31:0] dec_i0_csr_wrdata_wb, // csr write data at wb
output logic dec_i0_csr_is_mcpc_e4, // csr address is to MCPC
output logic [pt.NUM_THREADS-1:0] dec_csr_stall_int_ff, // csr is mie/mstatus
output logic dec_csr_nmideleg_e4, // csr is mnmipdel
// end CSR interface
output dec_tlu_i0_valid_e4, // i0 valid inst at e4
output dec_tlu_i1_valid_e4,
output eh2_trap_pkt_t dec_tlu_packet_e4, // trap packet
output logic [31:1] dec_tlu_i0_pc_e4, // i0 trap pc
output logic [31:1] dec_tlu_i1_pc_e4,
output logic [pt.NUM_THREADS-1:0][31:0] dec_illegal_inst,
output logic dec_i1_valid_e1, // i1 valid e1
output logic [pt.NUM_THREADS-1:0][31:1] pred_correct_npc_e2, // npc e2 if the prediction is correct
output logic dec_i0_rs1_bypass_en_e3, // i0 rs1 bypass enables e3
output logic dec_i0_rs2_bypass_en_e3, // i1 rs1 bypass enables e3
output logic dec_i1_rs1_bypass_en_e3,
output logic dec_i1_rs2_bypass_en_e3,
output logic [31:0] i0_rs1_bypass_data_e3, // i0 rs1 bypass data e3
output logic [31:0] i0_rs2_bypass_data_e3, // i1 rs1 bypass data e3
output logic [31:0] i1_rs1_bypass_data_e3,
output logic [31:0] i1_rs2_bypass_data_e3,
output logic dec_i0_sec_decode_e3, // i0 secondary alu e3
output logic dec_i1_sec_decode_e3, // i1 secondary alu e3
output logic [31:1] dec_i0_pc_e3, // i0 pc e3
output logic [31:1] dec_i1_pc_e3, // i1 pc e3
output logic dec_i0_rs1_bypass_en_e2, // i0 rs1 bypass enable e2
output logic dec_i0_rs2_bypass_en_e2, // i0 rs2 bypass enable e2
output logic dec_i1_rs1_bypass_en_e2,
output logic dec_i1_rs2_bypass_en_e2,
output logic [31:0] i0_rs1_bypass_data_e2, // i0 rs1 bypass data e2
output logic [31:0] i0_rs2_bypass_data_e2, // i0 rs2 bypass data e2
output logic [31:0] i1_rs1_bypass_data_e2,
output logic [31:0] i1_rs2_bypass_data_e2,
output eh2_predict_pkt_t i0_predict_p_d, // i0 predict packet decode
output eh2_predict_pkt_t i1_predict_p_d,
output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // i0 predict fghr
output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d, // i0 predict index
output logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d, // i0_predict branch tag
output logic [pt.BTB_TOFFSET_SIZE-1:0] i0_predict_toffset_d, // i0_predict branch tag
output logic [pt.BHT_GHR_SIZE-1:0] i1_predict_fghr_d, // i1 predict fghr
output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i1_predict_index_d, // i1 predict index
output logic [pt.BTB_BTAG_SIZE-1:0] i1_predict_btag_d, // i1_predict branch tag
output logic [pt.BTB_TOFFSET_SIZE-1:0] i1_predict_toffset_d, // i1_predict branch tag
output logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index
output logic [31:0] i0_result_e4_eff, // i0 e4 result
output logic [31:0] i1_result_e4_eff,
output logic [31:0] i0_result_e2, // i0 result e2
output logic [4:1] dec_i0_data_en, // clock-gating logic
output logic [4:1] dec_i0_ctl_en,
output logic [4:1] dec_i1_data_en,
output logic [4:1] dec_i1_ctl_en,
output logic [pt.NUM_THREADS-1:0][1:0] dec_pmu_instr_decoded, // number of instructions decode this cycle encoded
output logic [pt.NUM_THREADS-1:0] dec_pmu_decode_stall, // decode is stalled
output logic [pt.NUM_THREADS-1:0] dec_pmu_presync_stall, // decode has presync stall
output logic [pt.NUM_THREADS-1:0] dec_pmu_postsync_stall, // decode has postsync stall
output logic [pt.NUM_THREADS-1:0] dec_nonblock_load_wen, // write enable for nonblock load
output logic [pt.NUM_THREADS-1:0][4:0] dec_nonblock_load_waddr, // logical write addr for nonblock load
output logic [pt.NUM_THREADS-1:0] dec_pause_state, // core in pause state
output logic [pt.NUM_THREADS-1:0] dec_pause_state_cg, // core in pause state for clock-gating
output logic [pt.NUM_THREADS-1:0] dec_thread_stall_in, // thread is known to stall next cycle - eg pause
output logic dec_div_active, // non-block divide is active
output logic dec_div_tid, // non-block divide tid
output logic dec_force_favor_flip_d,
input logic scan_mode
);
eh2_dec_pkt_t i0_dp_raw, i0_dp;
eh2_dec_pkt_t i1_dp_raw, i1_dp;
logic [31:0] i0, i1;
logic i0_valid_d, i1_valid_d;
logic [31:0] i0_result_e1, i1_result_e1;
logic [31:0] i1_result_e2;
logic [31:0] i0_result_e3, i1_result_e3;
logic [31:0] i0_result_e4, i1_result_e4;
logic [31:0] i0_result_wb, i1_result_wb;
logic [31:1] i0_pc_e1, i1_pc_e1;
logic [31:1] i0_pc_e2, i1_pc_e2;
logic [31:1] i0_pc_e3, i1_pc_e3;
logic [31:1] i0_pc_e4, i1_pc_e4;
logic [9:0] i0_rs1bypass, i0_rs2bypass;
logic [9:0] i1_rs1bypass, i1_rs2bypass;
logic i0_jalimm20, i1_jalimm20;
logic i0_uiimm20, i1_uiimm20;
logic lsu_decode_d;
logic [31:0] i0_immed_d;
logic [31:0] i1_immed_d;
logic i0_presync;
logic i0_postsync;
logic [pt.NUM_THREADS-1:0] presync_stall;
logic [pt.NUM_THREADS-1:0] postsync_stall_in, postsync_stall;
logic [pt.NUM_THREADS-1:0] base_postsync_stall_in, base_postsync_stall;
logic [pt.NUM_THREADS-1:0] jal_postsync_stall_in, jal_postsync_stall;
logic [pt.NUM_THREADS-1:0] prior_inflight, prior_inflight_e1e3, prior_inflight_e1e4, prior_inflight_wb;
logic [pt.NUM_THREADS-1:0] prior_csr_write, prior_csr_write_e1e4;
logic prior_any_csr_write_any_thread, prior_any_csr_write_any_thread_e1e4;
logic i0_csr_clr_d, i0_csr_set_d, i0_csr_write_d;
logic i0_csr_clr_e1,i0_csr_set_e1,i0_csr_write_e1,i0_csr_imm_e1;
logic [31:0] i0_csr_mask_e1;
logic [31:0] i0_write_csr_data_e1;
logic [pt.NUM_THREADS-1:0][31:0] write_csr_data_in;
logic [pt.NUM_THREADS-1:0][31:0] write_csr_data;
logic [pt.NUM_THREADS-1:0] csr_data_wen;
logic [4:0] i0_csrimm_e1;
logic [31:0] i0_csr_rddata_e1;
logic i1_load_block_d;
logic i1_mul_block_d, i1_mul_block_thread_1cycle_d;
logic i1_load2_block_d;
logic i1_mul2_block_d;
logic mul_decode_d;
logic i0_legal, i1_legal;
logic [pt.NUM_THREADS-1:0] shift_illegal;
logic [pt.NUM_THREADS-1:0] illegal_inst_en;
logic [pt.NUM_THREADS-1:0] illegal_lockout_in, illegal_lockout;
logic i0_legal_decode_d, i1_legal_decode_d;
logic [31:0] i0_result_e3_final, i1_result_e3_final;
logic [31:0] i0_result_wb_raw, i1_result_wb_raw;
logic [pt.NUM_THREADS-1:0][pt.BTB_TOFFSET_SIZE:1] last_br_immed_d, last_br_immed_e1, last_br_immed_e2;
logic [pt.NUM_THREADS-1:0][31:1] last_pc_e2;
logic i1_depend_i0_d;
logic i0_rs1_depend_i0_e1, i0_rs1_depend_i0_e2, i0_rs1_depend_i0_e3, i0_rs1_depend_i0_e4, i0_rs1_depend_i0_wb;
logic i0_rs1_depend_i1_e1, i0_rs1_depend_i1_e2, i0_rs1_depend_i1_e3, i0_rs1_depend_i1_e4, i0_rs1_depend_i1_wb;
logic i0_rs2_depend_i0_e1, i0_rs2_depend_i0_e2, i0_rs2_depend_i0_e3, i0_rs2_depend_i0_e4, i0_rs2_depend_i0_wb;
logic i0_rs2_depend_i1_e1, i0_rs2_depend_i1_e2, i0_rs2_depend_i1_e3, i0_rs2_depend_i1_e4, i0_rs2_depend_i1_wb;
logic i1_rs1_depend_i0_e1, i1_rs1_depend_i0_e2, i1_rs1_depend_i0_e3, i1_rs1_depend_i0_e4, i1_rs1_depend_i0_wb;
logic i1_rs1_depend_i1_e1, i1_rs1_depend_i1_e2, i1_rs1_depend_i1_e3, i1_rs1_depend_i1_e4, i1_rs1_depend_i1_wb;
logic i1_rs2_depend_i0_e1, i1_rs2_depend_i0_e2, i1_rs2_depend_i0_e3, i1_rs2_depend_i0_e4, i1_rs2_depend_i0_wb;
logic i1_rs2_depend_i1_e1, i1_rs2_depend_i1_e2, i1_rs2_depend_i1_e3, i1_rs2_depend_i1_e4, i1_rs2_depend_i1_wb;
logic i1_rs1_depend_i0_d, i1_rs2_depend_i0_d;
logic i0_secondary_d, i1_secondary_d;
logic i0_secondary_block_d, i1_secondary_block_d;
logic non_block_case_d;
logic i0_div_decode_d;
logic [31:0] i0_result_e4_final, i1_result_e4_final;
logic i0_load_block_d;
logic i0_mul_block_d, i0_mul_block_thread_1cycle_d;
logic [3:0] i0_rs1_depth_d, i0_rs2_depth_d;
logic [3:0] i1_rs1_depth_d, i1_rs2_depth_d;
logic i0_rs1_match_e1_e2, i0_rs1_match_e1_e3;
logic i0_rs2_match_e1_e2, i0_rs2_match_e1_e3;
logic i1_rs1_match_e1_e2, i1_rs1_match_e1_e3;
logic i1_rs2_match_e1_e2, i1_rs2_match_e1_e3;
logic i0_amo_stall_d, i1_amo_stall_d;
logic i0_load_stall_d, i1_load_stall_d;
logic i0_store_stall_d, i1_store_stall_d;
logic i0_predict_nt, i0_predict_t;
logic i1_predict_nt, i1_predict_t;
logic i0_notbr_error, i0_br_toffset_error;
logic i1_notbr_error, i1_br_toffset_error;
logic i0_ret_error, i1_ret_error;
logic i0_br_error, i1_br_error;
logic i0_br_error_all, i1_br_error_all;
logic [pt.BTB_TOFFSET_SIZE-1:0] i0_br_offset, i1_br_offset;
logic [20:1] i0_pcall_imm, i1_pcall_imm; // predicted jal's
logic i0_pcall_raw, i1_pcall_raw;
logic i0_pcall_case, i1_pcall_case;
logic i0_pcall, i1_pcall;
logic i0_pja_raw, i1_pja_raw;
logic i0_pja_case, i1_pja_case;
logic i0_pja, i1_pja;
logic i0_pret_case, i1_pret_case;
logic i0_pret_raw, i0_pret;
logic i1_pret_raw, i1_pret;
logic i0_jal, i1_jal; // jal's that are not predicted
logic i0_predict_br, i1_predict_br;
logic [31:0] i1_result_wb_eff, i0_result_wb_eff;
logic [2:0] i1rs1_intra, i1rs2_intra;
logic i1_rs1_intra_bypass, i1_rs2_intra_bypass;
logic store_data_bypass_c1, store_data_bypass_c2;
logic [1:0] store_data_bypass_e4_c1, store_data_bypass_e4_c2, store_data_bypass_e4_c3;
logic store_data_bypass_i0_e2_c2;
eh2_class_pkt_t i0_rs1_class_d, i0_rs2_class_d;
eh2_class_pkt_t i1_rs1_class_d, i1_rs2_class_d;
eh2_class_pkt_t i0_dc, i0_e1c, i0_e2c, i0_e3c, i0_e4c, i0_wbc;
eh2_class_pkt_t i1_dc, i1_e1c, i1_e2c, i1_e3c, i1_e4c, i1_wbc;
logic i0_rs1_match_e1, i0_rs1_match_e2, i0_rs1_match_e3;
logic i1_rs1_match_e1, i1_rs1_match_e2, i1_rs1_match_e3;
logic i0_rs2_match_e1, i0_rs2_match_e2, i0_rs2_match_e3;
logic i1_rs2_match_e1, i1_rs2_match_e2, i1_rs2_match_e3;
logic i0_secondary_stall_d;
logic i0_ap_pc2, i0_ap_pc4;
logic i1_ap_pc2, i1_ap_pc4;
logic i0_rd_en_d;
logic i1_rd_en_d;
logic load_ldst_bypass_c1;
logic load_mul_rs1_bypass_e1;
logic load_mul_rs2_bypass_e1;
logic [pt.NUM_THREADS-1:0] leak1_i0_stall_in, leak1_i0_stall;
logic [pt.NUM_THREADS-1:0] leak1_i1_stall_in, leak1_i1_stall;
logic [pt.NUM_THREADS-1:0] leak1_mode;
logic i0_csr_write_only_d;
logic i0_any_csr_d;
logic [5:0] i0_pipe_en;
logic i0_e1_ctl_en, i0_e2_ctl_en, i0_e3_ctl_en, i0_e4_ctl_en, i0_wb_ctl_en;
logic i0_e1_data_en, i0_e2_data_en, i0_e3_data_en, i0_e4_data_en, i0_wb_data_en, i0_wb1_data_en;
logic [5:0] i1_pipe_en;
logic i1_e1_ctl_en, i1_e2_ctl_en, i1_e3_ctl_en, i1_e4_ctl_en, i1_wb_ctl_en;
logic i1_e1_data_en, i1_e2_data_en, i1_e3_data_en, i1_e4_data_en, i1_wb_data_en, i1_wb1_data_en;
logic debug_fence_i;
logic debug_fence;
logic i0_csr_write;
logic i0_instr_error;
logic i0_icaf_d;
logic i1_icaf_d;
logic i0_not_alu_eff, i1_not_alu_eff;
logic [pt.NUM_THREADS-1:0] clear_pause;
logic [pt.NUM_THREADS-1:0] pause_state_in, pause_state;
logic [pt.NUM_THREADS-1:0] pause_stall;
logic [31:1] i1_pc_wb;
logic i0_brp_valid;
logic [pt.NUM_THREADS-1:0] lsu_idle;
logic i0_csr_read_e1;
logic i0_block_d;
logic i1_block_d;
eh2_inst_pkt_t i0_itype, i1_itype;
logic i0_br_unpred, i1_br_unpred;
logic [pt.NUM_THREADS-1:0] flush_final_lower, flush_final_upper_e2;
eh2_reg_pkt_t i0r, i1r;
logic i1_cancel_d, i1_cancel_e1;
logic [4:0] nonblock_load_rd;
logic nonblock_load_tid_dc1;
logic i1_wen_wb, i0_wen_wb;
logic [pt.NUM_THREADS-1:0] [4:0] cam_nonblock_load_waddr;
logic [pt.NUM_THREADS-1:0] cam_nonblock_load_wen;
logic [pt.NUM_THREADS-1:0] cam_i0_nonblock_load_stall;
logic [pt.NUM_THREADS-1:0] cam_i1_nonblock_load_stall;
logic [pt.NUM_THREADS-1:0] cam_i0_load_kill_wen;
logic [pt.NUM_THREADS-1:0] cam_i1_load_kill_wen;
logic [pt.NUM_THREADS-1:0] tlu_wr_pause_wb1;
logic [pt.NUM_THREADS-1:0] tlu_wr_pause_wb2;
logic debug_fence_raw;
eh2_trap_pkt_t dt, e1t_in, e1t, e2t_in, e2t, e3t_in, e3t, e4t_ff, e4t;
logic [31:0] i0_inst_d, i1_inst_d;
logic [31:0] i0_inst_e1, i1_inst_e1;
logic [31:0] i0_inst_e2, i1_inst_e2;
logic [31:0] i0_inst_e3, i1_inst_e3;
logic [31:0] i0_inst_e4, i1_inst_e4;
logic [31:0] i0_inst_wb, i1_inst_wb;
logic [31:0] i0_inst_wb1,i1_inst_wb1;
eh2_dest_pkt_t dd, e1d, e2d, e3d, e4d, wbd;
eh2_class_pkt_t i0_e4c_in, i1_e4c_in;
eh2_dest_pkt_t e1d_in, e2d_in, e3d_in, e4d_in;
logic [31:1] i0_pc_wb, i0_pc_wb1;
logic [31:1] i1_pc_wb1;
logic [pt.NUM_THREADS-1:0][31:0] illegal_inst;
logic [pt.NUM_THREADS-1:0] i1_flush_final_e3;
logic [pt.NUM_THREADS-1:0] i0_flush_final_e4;
logic i1_block_same_thread_d;
logic [pt.NUM_THREADS-1:0] flush_lower_wb;
logic [pt.NUM_THREADS-1:0] flush_extint;
logic i0_csr_update_e1;
logic [pt.NUM_THREADS-1:0] csr_update_e1;
logic [pt.NUM_THREADS-1:0][31:0] write_csr_data_e1;
logic [pt.NUM_THREADS-1:0][31:0] write_csr_data_wb;
logic i0_csr_legal_d;
logic lsu_tid_e3;
logic div_stall;
logic div_tid;
logic div_active, div_active_in;
logic div_valid;
logic [4:0] div_rd;
logic i0_nonblock_div_stall, i1_nonblock_div_stall;
logic div_e1_to_wb;
logic div_flush;
logic nonblock_div_cancel;
logic i0_div_prior_div_stall;
logic i1_secondary_block_thread_1cycle_d, i0_secondary_block_thread_1cycle_d;
logic i1_secondary_block_thread_2cycle_d, i0_secondary_block_thread_2cycle_d;
logic i0_secondary_stall_1cycle_d, i0_secondary_stall_2cycle_d;
logic i0_secondary_stall_thread_1cycle_d, i0_secondary_stall_thread_2cycle_d;
logic i1_br_error_fast, i0_br_error_fast;
logic i0_atomic_legal;
logic i1_atomic_legal;
logic i0_bitmanip_zbb_legal;
logic i0_bitmanip_zbs_legal;
logic i0_bitmanip_zbe_legal;
logic i0_bitmanip_zbc_legal;
logic i0_bitmanip_zbp_legal;
logic i0_bitmanip_zbr_legal;
logic i0_bitmanip_zbf_legal;
logic i0_bitmanip_zba_legal;
logic i0_bitmanip_zbb_zbp_legal;
logic i0_bitmanip_zbp_zbe_zbf_legal;
logic i0_bitmanip_zbb_zbp_zbe_zbf_legal;
logic i0_bitmanip_legal;
logic i1_bitmanip_zbb_legal;
logic i1_bitmanip_zbs_legal;
logic i1_bitmanip_zbe_legal;
logic i1_bitmanip_zbc_legal;
logic i1_bitmanip_zbp_legal;
logic i1_bitmanip_zbr_legal;
logic i1_bitmanip_zbf_legal;
logic i1_bitmanip_zba_legal;
logic i1_bitmanip_zbb_zbp_legal;
logic i1_bitmanip_zbp_zbe_zbf_legal;
logic i1_bitmanip_zbb_zbp_zbe_zbf_legal;
logic i1_bitmanip_legal;
logic i0_legal_except_csr;
logic [pt.NUM_THREADS-1:0] flush_all;
logic [pt.NUM_THREADS-1:0] smt_secondary_stall_in, smt_secondary_stall, smt_secondary_stall_raw;
logic [pt.NUM_THREADS-1:0] set_smt_presync_stall;
logic [pt.NUM_THREADS-1:0] smt_presync_stall_in, smt_presync_stall, smt_presync_stall_raw;
logic [pt.NUM_THREADS-1:0] set_smt_csr_write_stall;
logic [pt.NUM_THREADS-1:0] smt_csr_write_stall_in, smt_csr_write_stall, smt_csr_write_stall_raw;
logic [pt.NUM_THREADS-1:0] set_smt_atomic_stall;
logic [pt.NUM_THREADS-1:0] smt_atomic_stall_in, smt_atomic_stall, smt_atomic_stall_raw;
logic [pt.NUM_THREADS-1:0] set_smt_div_stall;
logic [pt.NUM_THREADS-1:0] smt_div_stall_in, smt_div_stall, smt_div_stall_raw;
logic [pt.NUM_THREADS-1:0] set_smt_nonblock_load_stall;
logic [pt.NUM_THREADS-1:0] smt_nonblock_load_stall_in, smt_nonblock_load_stall, smt_nonblock_load_stall_raw;
logic [pt.NUM_THREADS-1:0] cam_nonblock_load_stall;
logic nonblock_load_tid_dc2, nonblock_load_tid_dc5, i0_rs1_nonblock_load_bypass_en_d, i0_rs2_nonblock_load_bypass_en_d, i1_rs1_nonblock_load_bypass_en_d, i1_rs2_nonblock_load_bypass_en_d;
typedef struct packed {
logic csr_read_stall;
logic extint_stall;
logic i1_cancel_e1_stall;
logic pause_stall;
logic leak1_stall;
logic debug_stall;
logic postsync_stall;
logic presync_stall;
logic wait_lsu_idle_stall;
logic nonblock_load_stall;
logic nonblock_div_stall;
logic prior_div_stall;
logic load_stall;
logic store_stall;
logic amo_stall;
logic load_block;
logic mul_block;
logic secondary_block;
logic secondary_stall;
} i0_block_pkt_t;
typedef struct packed {
logic debug_valid_stall;
logic nonblock_load_stall;
logic wait_lsu_idle_stall;
logic extint_stall;
logic i1_cancel_e1_stall;
logic pause_stall;
logic debug_stall;
logic postsync_stall;
logic presync_stall;
logic nonblock_div_stall;
logic load_stall;
logic store_stall;
logic amo_stall;
logic load_block;
logic mul_block;
logic load2_block;
logic mul2_block;
logic secondary_block;
logic leak1_stall;
logic i0_only_block;
logic icaf_block;
logic block_same_thread;
} i1_block_pkt_t;
i0_block_pkt_t i0blockp;
i1_block_pkt_t i1blockp;
logic i1_depend_i0_case_d;
logic i0_debug_valid_wb, i0_debug_valid_e4, i0_debug_valid_e3, i0_debug_valid_e2, i0_debug_valid_e1;
logic i1_pc4_e1, i0_pc4_e1;
logic i1_pc4_e2, i0_pc4_e2;
logic i1_pc4_e3, i0_pc4_e3;
// branch prediction
// in leak1_mode, ignore any predictions for i0, treat branch as if we haven't seen it before
// in leak1 mode, also ignore branch errors for i0
// qual i0_brp_valid with icaf; no need to qual i1_brp_valid since it wont decode if icaf
assign i0_brp_valid = dec_i0_brp.valid & ~leak1_mode[dd.i0tid] & ~i0_icaf_d;
always_comb begin
i0_predict_p_d = '0;
i0_predict_index_d[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = '0;
i0_predict_btag_d[pt.BTB_BTAG_SIZE-1:0] = '0;
i0_predict_toffset_d[pt.BTB_TOFFSET_SIZE-1:0] = '0;
i0_predict_fghr_d[pt.BHT_GHR_SIZE-1:0] = '0;
if (dec_i0_branch_d) begin
i0_predict_p_d.pcall = i0_pcall; // dont mark as pcall if branch error
i0_predict_p_d.pja = i0_pja;
i0_predict_p_d.pret = i0_pret;
i0_predict_p_d.prett[31:1] = dec_i0_brp.prett[31:1];
i0_predict_p_d.pc4 = dec_i0_pc4_d;
i0_predict_p_d.hist[1:0] = dec_i0_brp.hist[1:0];
i0_predict_p_d.valid = i0_brp_valid & i0_legal_decode_d;
i0_predict_p_d.br_error = i0_br_error & i0_legal_decode_d & ~leak1_mode[dd.i0tid];
i0_predict_p_d.br_start_error = dec_i0_brp.br_start_error & i0_legal_decode_d & ~leak1_mode[dd.i0tid];
i0_predict_p_d.bank = dec_i0_brp.bank;
i0_predict_p_d.way = dec_i0_brp.way;
i0_predict_index_d[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = dec_i0_bp_index;
i0_predict_btag_d[pt.BTB_BTAG_SIZE-1:0] = dec_i0_bp_btag[pt.BTB_BTAG_SIZE-1:0];
i0_predict_toffset_d[pt.BTB_TOFFSET_SIZE-1:0] = i0_br_offset[pt.BTB_TOFFSET_SIZE-1:0];
i0_predict_fghr_d[pt.BHT_GHR_SIZE-1:0] = dec_i0_bp_fghr[pt.BHT_GHR_SIZE-1:0];
end // if (dec_i0_branch_d)
end // always_comb begin
assign i0_notbr_error = i0_brp_valid & ~(i0_dp_raw.condbr | i0_pcall_raw | i0_pja_raw | i0_pret_raw);
// no toffset error for a pret
assign i0_br_toffset_error = i0_brp_valid & dec_i0_brp.hist[1] & (dec_i0_bp_toffset[pt.BTB_TOFFSET_SIZE-1:0] != i0_br_offset[pt.BTB_TOFFSET_SIZE-1:0]) & !i0_pret_raw;
assign i0_ret_error = i0_brp_valid & (dec_i0_brp.ret ^ i0_pret_raw);
assign i0_br_error = dec_i0_brp.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error;
assign i0_br_error_all = (i0_br_error | dec_i0_brp.br_start_error) & ~leak1_mode[dd.i0tid];
assign i0_br_error_fast = (dec_i0_brp.br_error | dec_i0_brp.br_start_error) & ~leak1_mode[dd.i0tid];
// errors go to i0 only
if(pt.BTB_FULLYA) begin
logic [pt.NUM_THREADS-1:0] i0_btb_error_found, i0_btb_error_found_f;
logic [pt.NUM_THREADS-1:0] [$clog2(pt.BTB_SIZE)-1:0] i0_fa_error_index_ns, dec_i0_fa_error_index;
for (genvar k=0; k<pt.NUM_THREADS; k++) begin : fa_error_index
assign i0_btb_error_found[k] = (dd.i0tid == k) & (i0_br_error_all | i0_btb_error_found_f[k]) & ~dec_tlu_flush_lower_wb[k];
assign i0_fa_error_index_ns[k] = ((dd.i0tid == k) & i0_br_error_all & ~i0_btb_error_found_f[k]) ? dec_i0_bp_fa_index : dec_i0_fa_error_index[k];
rvdff #($clog2(pt.BTB_SIZE)+1) btberrorfa_f (.*, .clk(active_clk),
.din({i0_btb_error_found[k], i0_fa_error_index_ns[k]}),
.dout({i0_btb_error_found_f[k], dec_i0_fa_error_index[k]}));
end
assign dec_fa_error_index = |dec_tlu_flush_lower_wb ? dec_i0_fa_error_index[wbd.i0tid] : '0;
end
else
assign dec_fa_error_index = 'b0;
always_comb begin
i1_predict_p_d = '0;
i1_predict_index_d[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = '0;
i1_predict_btag_d[pt.BTB_BTAG_SIZE-1:0] = '0;
i1_predict_toffset_d[pt.BTB_TOFFSET_SIZE-1:0] = '0;
i1_predict_fghr_d[pt.BHT_GHR_SIZE-1:0] = '0;
if (dec_i1_branch_d) begin
i1_predict_p_d.pcall = i1_pcall;
i1_predict_p_d.pja = i1_pja;
i1_predict_p_d.pret = i1_pret;
i1_predict_p_d.prett[31:1] = dec_i1_brp.prett[31:1];
i1_predict_p_d.pc4 = dec_i1_pc4_d;
i1_predict_p_d.hist[1:0] = dec_i1_brp.hist[1:0];
i1_predict_p_d.valid = dec_i1_brp.valid & i1_legal_decode_d;
i1_predict_p_d.br_error = i1_br_error & i1_legal_decode_d;
i1_predict_p_d.br_start_error = dec_i1_brp.br_start_error & i1_legal_decode_d;
i1_predict_p_d.bank = dec_i1_brp.bank;
i1_predict_p_d.way = dec_i1_brp.way;
i1_predict_index_d[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = dec_i1_bp_index;
i1_predict_btag_d[pt.BTB_BTAG_SIZE-1:0] = dec_i1_bp_btag[pt.BTB_BTAG_SIZE-1:0];
i1_predict_toffset_d[pt.BTB_TOFFSET_SIZE-1:0] = i1_br_offset[pt.BTB_TOFFSET_SIZE-1:0];
i1_predict_fghr_d[pt.BHT_GHR_SIZE-1:0] = dec_i1_bp_fghr[pt.BHT_GHR_SIZE-1:0];
end // if (dec_i1_branch_d)
end // always_comb begin
assign i1_notbr_error = dec_i1_brp.valid & ~(i1_dp_raw.condbr | i1_pcall_raw | i1_pja_raw | i1_pret_raw);
assign i1_br_toffset_error = dec_i1_brp.valid & dec_i1_brp.hist[1] & (dec_i1_bp_toffset[pt.BTB_TOFFSET_SIZE-1:0] != i1_br_offset[pt.BTB_TOFFSET_SIZE-1:0]) & !i1_pret_raw;
assign i1_ret_error = dec_i1_brp.valid & (dec_i1_brp.ret ^ i1_pret_raw);
assign i1_br_error = dec_i1_brp.br_error | i1_notbr_error | i1_br_toffset_error | i1_ret_error;
assign i1_br_error_all = (i1_br_error | dec_i1_brp.br_start_error);
assign i1_br_error_fast = (dec_i1_brp.br_error | dec_i1_brp.br_start_error);
// end
// on br error turn anything into a nop
// on i0 instruction fetch access fault turn anything into a nop
// nop => alu rs1 imm12 rd lor
assign i0_icaf_d = dec_i0_icaf_d | dec_i0_dbecc_d;
assign i1_icaf_d = dec_i1_icaf_d | dec_i1_dbecc_d;
assign i0_instr_error = i0_icaf_d;
always_comb begin
i0_dp = i0_dp_raw;
if (i0_br_error_fast | i0_instr_error) begin
i0_dp = '0;
i0_dp.alu = 1'b1;
i0_dp.rs1 = 1'b1;
i0_dp.rs2 = 1'b1;
i0_dp.lor = 1'b1;
i0_dp.legal = 1'b1;
end
i1_dp = i1_dp_raw;
if (i1_br_error_fast) begin
i1_dp = '0;
i1_dp.alu = 1'b1;
i1_dp.rs1 = 1'b1;
i1_dp.rs2 = 1'b1;
i1_dp.lor = 1'b1;
i1_dp.legal = 1'b1;
end
end
assign flush_lower_wb[pt.NUM_THREADS-1:0] = dec_tlu_flush_lower_wb[pt.NUM_THREADS-1:0];
assign i0[31:0] = dec_i0_instr_d[31:0];
assign i1[31:0] = dec_i1_instr_d[31:0];
assign dec_i0_select_pc_d = i0_dp.pc;
assign dec_i1_select_pc_d = i1_dp.pc;
// branches that can be predicted
assign i0_predict_br = i0_dp.condbr | i0_pcall | i0_pja | i0_pret;
assign i1_predict_br = i1_dp.condbr | i1_pcall | i1_pja | i1_pret;
assign i0_predict_nt = ~(dec_i0_brp.hist[1] & i0_brp_valid) & i0_predict_br;
assign i0_predict_t = (dec_i0_brp.hist[1] & i0_brp_valid) & i0_predict_br;
always_comb begin
i0_ap = '0;
i0_ap.tid = dd.i0tid;
if (i0_dp.legal & i0_dp.alu & i0_valid_d) begin
i0_ap.add = i0_dp.add;
i0_ap.sub = i0_dp.sub;
i0_ap.land = i0_dp.land;
i0_ap.lor = i0_dp.lor;
i0_ap.lxor = i0_dp.lxor;
i0_ap.sll = i0_dp.sll;
i0_ap.srl = i0_dp.srl;
i0_ap.sra = i0_dp.sra;
i0_ap.slt = i0_dp.slt;
i0_ap.unsign = i0_dp.unsign;
i0_ap.beq = i0_dp.beq;
i0_ap.bne = i0_dp.bne;
i0_ap.blt = i0_dp.blt;
i0_ap.bge = i0_dp.bge;
i0_ap.clz = i0_dp.clz;
i0_ap.ctz = i0_dp.ctz;
i0_ap.cpop = i0_dp.cpop;
i0_ap.sext_b = i0_dp.sext_b;
i0_ap.sext_h = i0_dp.sext_h;
i0_ap.sh1add = i0_dp.sh1add;
i0_ap.sh2add = i0_dp.sh2add;
i0_ap.sh3add = i0_dp.sh3add;
i0_ap.zba = i0_dp.zba;
i0_ap.min = i0_dp.min;
i0_ap.max = i0_dp.max;
i0_ap.pack = i0_dp.pack;
i0_ap.packu = i0_dp.packu;
i0_ap.packh = i0_dp.packh;
i0_ap.rol = i0_dp.rol;
i0_ap.ror = i0_dp.ror;
i0_ap.grev = i0_dp.grev;
i0_ap.gorc = i0_dp.gorc;
i0_ap.zbb = i0_dp.zbb;
i0_ap.bset = i0_dp.bset;
i0_ap.bclr = i0_dp.bclr;
i0_ap.binv = i0_dp.binv;
i0_ap.bext = i0_dp.bext;
i0_ap.csr_write = i0_csr_write_only_d;
i0_ap.csr_imm = i0_dp.csr_imm;
i0_ap.jal = i0_jal;