VerilatorTB problem

[togetherwhenyouwant]

when i run this command:
make -f $RV_ROOT/tools/Makefile target=default_mt

only get:
VerilatorTB: Start of sim

----------------------------------------
Hello World from SweRV EH2 hart0 @WDC !!
----------------------------------------
TEST_PASSED

Finished hart0 : minstret = 524, mcycle = 1492
Finished hart1 : minstret = 1227, mcycle = 1424
See "exec.log" for execution trace with register updates..

- /home/lyj/Cores-SweRV-EH2-master/testbench/tb_top.sv:337: Verilog $finish

VerilatorTB: End of sim

but not get:

VerilatorTB: Start of sim

----------------------------------------
Hello World from SweRV EH2 hart0 @WDC !!
----------------------------------------
----------------------------------------
Hello World from SweRV EH2 hart1 @WDC !!
----------------------------------------
TEST_PASSED

Finished hart0 : minstret = 1158, mcycle = 2895
Finished hart1 : minstret = 1733, mcycle = 2822
See "exec.log" for execution trace with register updates..

the system run out when exec to this line:

[agrobman]

Just ran it:

./obj_dir/Vtb_top 

VerilatorTB: Start of sim

----------------------------------------
Hello World from SweRV EH2 hart0 @WDC !!
----------------------------------------
----------------------------------------
Hello World from SweRV EH2 hart1 @WDC !!
----------------------------------------
TEST_PASSED

Finished hart0 : minstret = 1164, mcycle = 2913
Finished hart1 : minstret = 1735, mcycle = 2845
See "exec.log" for execution trace with register updates..

You probably have no RISCV tools installed and the make runs simulation with precompiled hex files.

try following commands:

rm *.hex
make -f $RV_ROOT/tools/Makefile target=default_mt verilator TEST=hello_world_mt GCC_PREFIX=kuku