Issue in running the Design in vivado

[rajat-agnisys]

Hello,

I am just trying to run swerv design on xilinx zed board using vivado and instead of running it in the debug mode using jtag and uart i want to interface this with zedboard io's.
Could you help me in this as i am unable to write firmware sequences for the swerv core in fpga or how to initialize the memory with those hardcode sequence.

Thanks

[aprnath]

Hi Rajat, we could not understand exactly what is being asked/requested here. If this is still an issue blocking you please open a new issue and we can try to understand your use case.