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FPU.fir
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FPU.fir
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circuit FPU :
module FPU :
input clock : Clock
input reset : UInt<1>
output io : {flip inst : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, store_data : UInt<64>, toint_data : UInt<64>, flip dmem_resp_val : UInt<1>, flip dmem_resp_type : UInt<3>, flip dmem_resp_tag : UInt<5>, flip dmem_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>, flip cp_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, cp_resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}}
io is invalid
io is invalid
reg ex_reg_valid : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[FPU.scala 509:25]
ex_reg_valid <= io.valid @[FPU.scala 509:25]
node req_valid = or(ex_reg_valid, io.cp_req.valid) @[FPU.scala 510:32]
reg ex_reg_inst : UInt<32>, clock @[Reg.scala 34:16]
when io.valid : @[Reg.scala 35:19]
ex_reg_inst <= io.inst @[Reg.scala 35:23]
skip @[Reg.scala 35:19]
node ex_cp_valid = and(io.cp_req.ready, io.cp_req.valid) @[Decoupled.scala 30:37]
node _T_215 = eq(io.killx, UInt<1>("h00")) @[FPU.scala 513:48]
node _T_216 = and(ex_reg_valid, _T_215) @[FPU.scala 513:45]
node _T_217 = or(_T_216, ex_cp_valid) @[FPU.scala 513:58]
reg mem_reg_valid : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[FPU.scala 513:26]
mem_reg_valid <= _T_217 @[FPU.scala 513:26]
reg mem_reg_inst : UInt<32>, clock @[Reg.scala 34:16]
when ex_reg_valid : @[Reg.scala 35:19]
mem_reg_inst <= ex_reg_inst @[Reg.scala 35:23]
skip @[Reg.scala 35:19]
reg mem_cp_valid : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[FPU.scala 515:25]
mem_cp_valid <= ex_cp_valid @[FPU.scala 515:25]
node _T_221 = or(io.killm, io.nack_mem) @[FPU.scala 516:25]
node _T_223 = eq(mem_cp_valid, UInt<1>("h00")) @[FPU.scala 516:44]
node killm = and(_T_221, _T_223) @[FPU.scala 516:41]
node _T_225 = eq(killm, UInt<1>("h00")) @[FPU.scala 517:49]
node _T_226 = or(_T_225, mem_cp_valid) @[FPU.scala 517:56]
node _T_227 = and(mem_reg_valid, _T_226) @[FPU.scala 517:45]
reg wb_reg_valid : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[FPU.scala 517:25]
wb_reg_valid <= _T_227 @[FPU.scala 517:25]
reg wb_cp_valid : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[FPU.scala 518:24]
wb_cp_valid <= mem_cp_valid @[FPU.scala 518:24]
inst fp_decoder of FPUDecoder @[FPU.scala 520:26]
fp_decoder.io is invalid
fp_decoder.clock <= clock
fp_decoder.reset <= reset
fp_decoder.io.inst <= io.inst @[FPU.scala 521:22]
wire cp_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>} @[FPU.scala 523:21]
cp_ctrl is invalid @[FPU.scala 523:21]
cp_ctrl <- io.cp_req.bits @[FPU.scala 524:11]
io.cp_resp.valid <= UInt<1>("h00") @[FPU.scala 525:20]
io.cp_resp.bits.data <= UInt<1>("h00") @[FPU.scala 526:24]
reg _T_282 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>}, clock @[Reg.scala 34:16]
when io.valid : @[Reg.scala 35:19]
_T_282 <- fp_decoder.io.sigs @[Reg.scala 35:23]
skip @[Reg.scala 35:19]
node ex_ctrl = mux(ex_cp_valid, cp_ctrl, _T_282) @[FPU.scala 529:20]
reg mem_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>}, clock @[Reg.scala 34:16]
when req_valid : @[Reg.scala 35:19]
mem_ctrl <- ex_ctrl @[Reg.scala 35:23]
skip @[Reg.scala 35:19]
reg wb_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>}, clock @[Reg.scala 34:16]
when mem_reg_valid : @[Reg.scala 35:19]
wb_ctrl <- mem_ctrl @[Reg.scala 35:23]
skip @[Reg.scala 35:19]
reg load_wb : UInt<1>, clock @[FPU.scala 534:20]
load_wb <= io.dmem_resp_val @[FPU.scala 534:20]
node _T_381 = bits(io.dmem_resp_type, 0, 0) @[FPU.scala 535:52]
node _T_383 = eq(_T_381, UInt<1>("h00")) @[FPU.scala 535:34]
reg load_wb_single : UInt<1>, clock @[Reg.scala 34:16]
when io.dmem_resp_val : @[Reg.scala 35:19]
load_wb_single <= _T_383 @[Reg.scala 35:23]
skip @[Reg.scala 35:19]
reg load_wb_data : UInt<64>, clock @[Reg.scala 34:16]
when io.dmem_resp_val : @[Reg.scala 35:19]
load_wb_data <= io.dmem_resp_data @[Reg.scala 35:23]
skip @[Reg.scala 35:19]
reg load_wb_tag : UInt<5>, clock @[Reg.scala 34:16]
when io.dmem_resp_val : @[Reg.scala 35:19]
load_wb_tag <= io.dmem_resp_tag @[Reg.scala 35:23]
skip @[Reg.scala 35:19]
node _T_387 = bits(load_wb_data, 31, 31) @[recFNFromFN.scala 47:22]
node _T_388 = bits(load_wb_data, 30, 23) @[recFNFromFN.scala 48:23]
node _T_389 = bits(load_wb_data, 22, 0) @[recFNFromFN.scala 49:25]
node _T_391 = eq(_T_388, UInt<1>("h00")) @[recFNFromFN.scala 51:34]
node _T_393 = eq(_T_389, UInt<1>("h00")) @[recFNFromFN.scala 52:38]
node _T_394 = and(_T_391, _T_393) @[recFNFromFN.scala 53:34]
node _T_395 = shl(_T_389, 9) @[recFNFromFN.scala 56:26]
node _T_396 = bits(_T_395, 31, 16) @[CircuitMath.scala 35:17]
node _T_397 = bits(_T_395, 15, 0) @[CircuitMath.scala 36:17]
node _T_399 = neq(_T_396, UInt<1>("h00")) @[CircuitMath.scala 37:22]
node _T_400 = bits(_T_396, 15, 8) @[CircuitMath.scala 35:17]
node _T_401 = bits(_T_396, 7, 0) @[CircuitMath.scala 36:17]
node _T_403 = neq(_T_400, UInt<1>("h00")) @[CircuitMath.scala 37:22]
node _T_404 = bits(_T_400, 7, 4) @[CircuitMath.scala 35:17]
node _T_405 = bits(_T_400, 3, 0) @[CircuitMath.scala 36:17]
node _T_407 = neq(_T_404, UInt<1>("h00")) @[CircuitMath.scala 37:22]
node _T_408 = bits(_T_404, 3, 3) @[CircuitMath.scala 32:12]
node _T_410 = bits(_T_404, 2, 2) @[CircuitMath.scala 32:12]
node _T_412 = bits(_T_404, 1, 1) @[CircuitMath.scala 30:8]
node _T_413 = mux(_T_410, UInt<2>("h02"), _T_412) @[CircuitMath.scala 32:10]
node _T_414 = mux(_T_408, UInt<2>("h03"), _T_413) @[CircuitMath.scala 32:10]
node _T_415 = bits(_T_405, 3, 3) @[CircuitMath.scala 32:12]
node _T_417 = bits(_T_405, 2, 2) @[CircuitMath.scala 32:12]
node _T_419 = bits(_T_405, 1, 1) @[CircuitMath.scala 30:8]
node _T_420 = mux(_T_417, UInt<2>("h02"), _T_419) @[CircuitMath.scala 32:10]
node _T_421 = mux(_T_415, UInt<2>("h03"), _T_420) @[CircuitMath.scala 32:10]
node _T_422 = mux(_T_407, _T_414, _T_421) @[CircuitMath.scala 38:21]
node _T_423 = cat(_T_407, _T_422) @[Cat.scala 30:58]
node _T_424 = bits(_T_401, 7, 4) @[CircuitMath.scala 35:17]
node _T_425 = bits(_T_401, 3, 0) @[CircuitMath.scala 36:17]
node _T_427 = neq(_T_424, UInt<1>("h00")) @[CircuitMath.scala 37:22]
node _T_428 = bits(_T_424, 3, 3) @[CircuitMath.scala 32:12]
node _T_430 = bits(_T_424, 2, 2) @[CircuitMath.scala 32:12]
node _T_432 = bits(_T_424, 1, 1) @[CircuitMath.scala 30:8]
node _T_433 = mux(_T_430, UInt<2>("h02"), _T_432) @[CircuitMath.scala 32:10]
node _T_434 = mux(_T_428, UInt<2>("h03"), _T_433) @[CircuitMath.scala 32:10]
node _T_435 = bits(_T_425, 3, 3) @[CircuitMath.scala 32:12]
node _T_437 = bits(_T_425, 2, 2) @[CircuitMath.scala 32:12]
node _T_439 = bits(_T_425, 1, 1) @[CircuitMath.scala 30:8]
node _T_440 = mux(_T_437, UInt<2>("h02"), _T_439) @[CircuitMath.scala 32:10]
node _T_441 = mux(_T_435, UInt<2>("h03"), _T_440) @[CircuitMath.scala 32:10]
node _T_442 = mux(_T_427, _T_434, _T_441) @[CircuitMath.scala 38:21]
node _T_443 = cat(_T_427, _T_442) @[Cat.scala 30:58]
node _T_444 = mux(_T_403, _T_423, _T_443) @[CircuitMath.scala 38:21]
node _T_445 = cat(_T_403, _T_444) @[Cat.scala 30:58]
node _T_446 = bits(_T_397, 15, 8) @[CircuitMath.scala 35:17]
node _T_447 = bits(_T_397, 7, 0) @[CircuitMath.scala 36:17]
node _T_449 = neq(_T_446, UInt<1>("h00")) @[CircuitMath.scala 37:22]
node _T_450 = bits(_T_446, 7, 4) @[CircuitMath.scala 35:17]
node _T_451 = bits(_T_446, 3, 0) @[CircuitMath.scala 36:17]
node _T_453 = neq(_T_450, UInt<1>("h00")) @[CircuitMath.scala 37:22]
node _T_454 = bits(_T_450, 3, 3) @[CircuitMath.scala 32:12]
node _T_456 = bits(_T_450, 2, 2) @[CircuitMath.scala 32:12]
node _T_458 = bits(_T_450, 1, 1) @[CircuitMath.scala 30:8]
node _T_459 = mux(_T_456, UInt<2>("h02"), _T_458) @[CircuitMath.scala 32:10]
node _T_460 = mux(_T_454, UInt<2>("h03"), _T_459) @[CircuitMath.scala 32:10]
node _T_461 = bits(_T_451, 3, 3) @[CircuitMath.scala 32:12]
node _T_463 = bits(_T_451, 2, 2) @[CircuitMath.scala 32:12]
node _T_465 = bits(_T_451, 1, 1) @[CircuitMath.scala 30:8]
node _T_466 = mux(_T_463, UInt<2>("h02"), _T_465) @[CircuitMath.scala 32:10]
node _T_467 = mux(_T_461, UInt<2>("h03"), _T_466) @[CircuitMath.scala 32:10]
node _T_468 = mux(_T_453, _T_460, _T_467) @[CircuitMath.scala 38:21]
node _T_469 = cat(_T_453, _T_468) @[Cat.scala 30:58]
node _T_470 = bits(_T_447, 7, 4) @[CircuitMath.scala 35:17]
node _T_471 = bits(_T_447, 3, 0) @[CircuitMath.scala 36:17]
node _T_473 = neq(_T_470, UInt<1>("h00")) @[CircuitMath.scala 37:22]
node _T_474 = bits(_T_470, 3, 3) @[CircuitMath.scala 32:12]
node _T_476 = bits(_T_470, 2, 2) @[CircuitMath.scala 32:12]
node _T_478 = bits(_T_470, 1, 1) @[CircuitMath.scala 30:8]
node _T_479 = mux(_T_476, UInt<2>("h02"), _T_478) @[CircuitMath.scala 32:10]
node _T_480 = mux(_T_474, UInt<2>("h03"), _T_479) @[CircuitMath.scala 32:10]
node _T_481 = bits(_T_471, 3, 3) @[CircuitMath.scala 32:12]
node _T_483 = bits(_T_471, 2, 2) @[CircuitMath.scala 32:12]
node _T_485 = bits(_T_471, 1, 1) @[CircuitMath.scala 30:8]
node _T_486 = mux(_T_483, UInt<2>("h02"), _T_485) @[CircuitMath.scala 32:10]
node _T_487 = mux(_T_481, UInt<2>("h03"), _T_486) @[CircuitMath.scala 32:10]
node _T_488 = mux(_T_473, _T_480, _T_487) @[CircuitMath.scala 38:21]
node _T_489 = cat(_T_473, _T_488) @[Cat.scala 30:58]
node _T_490 = mux(_T_449, _T_469, _T_489) @[CircuitMath.scala 38:21]
node _T_491 = cat(_T_449, _T_490) @[Cat.scala 30:58]
node _T_492 = mux(_T_399, _T_445, _T_491) @[CircuitMath.scala 38:21]
node _T_493 = cat(_T_399, _T_492) @[Cat.scala 30:58]
node _T_494 = not(_T_493) @[recFNFromFN.scala 56:13]
node _T_495 = dshl(_T_389, _T_494) @[recFNFromFN.scala 58:25]
node _T_496 = bits(_T_495, 21, 0) @[recFNFromFN.scala 58:37]
node _T_498 = cat(_T_496, UInt<1>("h00")) @[Cat.scala 30:58]
node _T_503 = mux(UInt<1>("h01"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 71:12]
node _T_504 = xor(_T_494, _T_503) @[recFNFromFN.scala 62:27]
node _T_505 = mux(_T_391, _T_504, _T_388) @[recFNFromFN.scala 61:16]
node _T_509 = mux(_T_391, UInt<2>("h02"), UInt<1>("h01")) @[recFNFromFN.scala 64:47]
node _T_510 = or(UInt<8>("h080"), _T_509) @[recFNFromFN.scala 64:42]
node _T_511 = add(_T_505, _T_510) @[recFNFromFN.scala 64:15]
node _T_512 = tail(_T_511, 1) @[recFNFromFN.scala 64:15]
node _T_513 = bits(_T_512, 8, 7) @[recFNFromFN.scala 67:25]
node _T_515 = eq(_T_513, UInt<2>("h03")) @[recFNFromFN.scala 67:50]
node _T_517 = eq(_T_393, UInt<1>("h00")) @[recFNFromFN.scala 68:17]
node _T_518 = and(_T_515, _T_517) @[recFNFromFN.scala 67:63]
node _T_519 = bits(_T_394, 0, 0) @[Bitwise.scala 71:15]
node _T_522 = mux(_T_519, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 71:12]
node _T_523 = shl(_T_522, 6) @[recFNFromFN.scala 71:45]
node _T_524 = not(_T_523) @[recFNFromFN.scala 71:28]
node _T_525 = and(_T_512, _T_524) @[recFNFromFN.scala 71:26]
node _T_526 = shl(_T_518, 6) @[recFNFromFN.scala 72:22]
node _T_527 = or(_T_525, _T_526) @[recFNFromFN.scala 71:64]
node _T_528 = mux(_T_391, _T_498, _T_389) @[recFNFromFN.scala 73:27]
node _T_529 = cat(_T_387, _T_527) @[Cat.scala 30:58]
node rec_s = cat(_T_529, _T_528) @[Cat.scala 30:58]
node _T_530 = bits(load_wb_data, 63, 63) @[recFNFromFN.scala 47:22]
node _T_531 = bits(load_wb_data, 62, 52) @[recFNFromFN.scala 48:23]
node _T_532 = bits(load_wb_data, 51, 0) @[recFNFromFN.scala 49:25]
node _T_534 = eq(_T_531, UInt<1>("h00")) @[recFNFromFN.scala 51:34]
node _T_536 = eq(_T_532, UInt<1>("h00")) @[recFNFromFN.scala 52:38]
node _T_537 = and(_T_534, _T_536) @[recFNFromFN.scala 53:34]
node _T_538 = shl(_T_532, 12) @[recFNFromFN.scala 56:26]
node _T_539 = bits(_T_538, 63, 32) @[CircuitMath.scala 35:17]
node _T_540 = bits(_T_538, 31, 0) @[CircuitMath.scala 36:17]
node _T_542 = neq(_T_539, UInt<1>("h00")) @[CircuitMath.scala 37:22]
node _T_543 = bits(_T_539, 31, 16) @[CircuitMath.scala 35:17]
node _T_544 = bits(_T_539, 15, 0) @[CircuitMath.scala 36:17]
node _T_546 = neq(_T_543, UInt<1>("h00")) @[CircuitMath.scala 37:22]
node _T_547 = bits(_T_543, 15, 8) @[CircuitMath.scala 35:17]
node _T_548 = bits(_T_543, 7, 0) @[CircuitMath.scala 36:17]
node _T_550 = neq(_T_547, UInt<1>("h00")) @[CircuitMath.scala 37:22]
node _T_551 = bits(_T_547, 7, 4) @[CircuitMath.scala 35:17]
node _T_552 = bits(_T_547, 3, 0) @[CircuitMath.scala 36:17]
node _T_554 = neq(_T_551, UInt<1>("h00")) @[CircuitMath.scala 37:22]
node _T_555 = bits(_T_551, 3, 3) @[CircuitMath.scala 32:12]
node _T_557 = bits(_T_551, 2, 2) @[CircuitMath.scala 32:12]
node _T_559 = bits(_T_551, 1, 1) @[CircuitMath.scala 30:8]
node _T_560 = mux(_T_557, UInt<2>("h02"), _T_559) @[CircuitMath.scala 32:10]
node _T_561 = mux(_T_555, UInt<2>("h03"), _T_560) @[CircuitMath.scala 32:10]
node _T_562 = bits(_T_552, 3, 3) @[CircuitMath.scala 32:12]
node _T_564 = bits(_T_552, 2, 2) @[CircuitMath.scala 32:12]
node _T_566 = bits(_T_552, 1, 1) @[CircuitMath.scala 30:8]
node _T_567 = mux(_T_564, UInt<2>("h02"), _T_566) @[CircuitMath.scala 32:10]
node _T_568 = mux(_T_562, UInt<2>("h03"), _T_567) @[CircuitMath.scala 32:10]
node _T_569 = mux(_T_554, _T_561, _T_568) @[CircuitMath.scala 38:21]
node _T_570 = cat(_T_554, _T_569) @[Cat.scala 30:58]
node _T_571 = bits(_T_548, 7, 4) @[CircuitMath.scala 35:17]
node _T_572 = bits(_T_548, 3, 0) @[CircuitMath.scala 36:17]
node _T_574 = neq(_T_571, UInt<1>("h00")) @[CircuitMath.scala 37:22]
node _T_575 = bits(_T_571, 3, 3) @[CircuitMath.scala 32:12]
node _T_577 = bits(_T_571, 2, 2) @[CircuitMath.scala 32:12]
node _T_579 = bits(_T_571, 1, 1) @[CircuitMath.scala 30:8]
node _T_580 = mux(_T_577, UInt<2>("h02"), _T_579) @[CircuitMath.scala 32:10]
node _T_581 = mux(_T_575, UInt<2>("h03"), _T_580) @[CircuitMath.scala 32:10]
node _T_582 = bits(_T_572, 3, 3) @[CircuitMath.scala 32:12]
node _T_584 = bits(_T_572, 2, 2) @[CircuitMath.scala 32:12]
node _T_586 = bits(_T_572, 1, 1) @[CircuitMath.scala 30:8]
node _T_587 = mux(_T_584, UInt<2>("h02"), _T_586) @[CircuitMath.scala 32:10]
node _T_588 = mux(_T_582, UInt<2>("h03"), _T_587) @[CircuitMath.scala 32:10]
node _T_589 = mux(_T_574, _T_581, _T_588) @[CircuitMath.scala 38:21]
node _T_590 = cat(_T_574, _T_589) @[Cat.scala 30:58]
node _T_591 = mux(_T_550, _T_570, _T_590) @[CircuitMath.scala 38:21]
node _T_592 = cat(_T_550, _T_591) @[Cat.scala 30:58]
node _T_593 = bits(_T_544, 15, 8) @[CircuitMath.scala 35:17]
node _T_594 = bits(_T_544, 7, 0) @[CircuitMath.scala 36:17]
node _T_596 = neq(_T_593, UInt<1>("h00")) @[CircuitMath.scala 37:22]
node _T_597 = bits(_T_593, 7, 4) @[CircuitMath.scala 35:17]
node _T_598 = bits(_T_593, 3, 0) @[CircuitMath.scala 36:17]
node _T_600 = neq(_T_597, UInt<1>("h00")) @[CircuitMath.scala 37:22]
node _T_601 = bits(_T_597, 3, 3) @[CircuitMath.scala 32:12]
node _T_603 = bits(_T_597, 2, 2) @[CircuitMath.scala 32:12]
node _T_605 = bits(_T_597, 1, 1) @[CircuitMath.scala 30:8]
node _T_606 = mux(_T_603, UInt<2>("h02"), _T_605) @[CircuitMath.scala 32:10]
node _T_607 = mux(_T_601, UInt<2>("h03"), _T_606) @[CircuitMath.scala 32:10]
node _T_608 = bits(_T_598, 3, 3) @[CircuitMath.scala 32:12]
node _T_610 = bits(_T_598, 2, 2) @[CircuitMath.scala 32:12]
node _T_612 = bits(_T_598, 1, 1) @[CircuitMath.scala 30:8]
node _T_613 = mux(_T_610, UInt<2>("h02"), _T_612) @[CircuitMath.scala 32:10]
node _T_614 = mux(_T_608, UInt<2>("h03"), _T_613) @[CircuitMath.scala 32:10]
node _T_615 = mux(_T_600, _T_607, _T_614) @[CircuitMath.scala 38:21]
node _T_616 = cat(_T_600, _T_615) @[Cat.scala 30:58]
node _T_617 = bits(_T_594, 7, 4) @[CircuitMath.scala 35:17]
node _T_618 = bits(_T_594, 3, 0) @[CircuitMath.scala 36:17]
node _T_620 = neq(_T_617, UInt<1>("h00")) @[CircuitMath.scala 37:22]
node _T_621 = bits(_T_617, 3, 3) @[CircuitMath.scala 32:12]
node _T_623 = bits(_T_617, 2, 2) @[CircuitMath.scala 32:12]
node _T_625 = bits(_T_617, 1, 1) @[CircuitMath.scala 30:8]
node _T_626 = mux(_T_623, UInt<2>("h02"), _T_625) @[CircuitMath.scala 32:10]
node _T_627 = mux(_T_621, UInt<2>("h03"), _T_626) @[CircuitMath.scala 32:10]
node _T_628 = bits(_T_618, 3, 3) @[CircuitMath.scala 32:12]
node _T_630 = bits(_T_618, 2, 2) @[CircuitMath.scala 32:12]
node _T_632 = bits(_T_618, 1, 1) @[CircuitMath.scala 30:8]
node _T_633 = mux(_T_630, UInt<2>("h02"), _T_632) @[CircuitMath.scala 32:10]
node _T_634 = mux(_T_628, UInt<2>("h03"), _T_633) @[CircuitMath.scala 32:10]
node _T_635 = mux(_T_620, _T_627, _T_634) @[CircuitMath.scala 38:21]
node _T_636 = cat(_T_620, _T_635) @[Cat.scala 30:58]
node _T_637 = mux(_T_596, _T_616, _T_636) @[CircuitMath.scala 38:21]
node _T_638 = cat(_T_596, _T_637) @[Cat.scala 30:58]
node _T_639 = mux(_T_546, _T_592, _T_638) @[CircuitMath.scala 38:21]
node _T_640 = cat(_T_546, _T_639) @[Cat.scala 30:58]
node _T_641 = bits(_T_540, 31, 16) @[CircuitMath.scala 35:17]
node _T_642 = bits(_T_540, 15, 0) @[CircuitMath.scala 36:17]
node _T_644 = neq(_T_641, UInt<1>("h00")) @[CircuitMath.scala 37:22]
node _T_645 = bits(_T_641, 15, 8) @[CircuitMath.scala 35:17]
node _T_646 = bits(_T_641, 7, 0) @[CircuitMath.scala 36:17]
node _T_648 = neq(_T_645, UInt<1>("h00")) @[CircuitMath.scala 37:22]
node _T_649 = bits(_T_645, 7, 4) @[CircuitMath.scala 35:17]
node _T_650 = bits(_T_645, 3, 0) @[CircuitMath.scala 36:17]
node _T_652 = neq(_T_649, UInt<1>("h00")) @[CircuitMath.scala 37:22]
node _T_653 = bits(_T_649, 3, 3) @[CircuitMath.scala 32:12]
node _T_655 = bits(_T_649, 2, 2) @[CircuitMath.scala 32:12]
node _T_657 = bits(_T_649, 1, 1) @[CircuitMath.scala 30:8]
node _T_658 = mux(_T_655, UInt<2>("h02"), _T_657) @[CircuitMath.scala 32:10]
node _T_659 = mux(_T_653, UInt<2>("h03"), _T_658) @[CircuitMath.scala 32:10]
node _T_660 = bits(_T_650, 3, 3) @[CircuitMath.scala 32:12]
node _T_662 = bits(_T_650, 2, 2) @[CircuitMath.scala 32:12]
node _T_664 = bits(_T_650, 1, 1) @[CircuitMath.scala 30:8]
node _T_665 = mux(_T_662, UInt<2>("h02"), _T_664) @[CircuitMath.scala 32:10]
node _T_666 = mux(_T_660, UInt<2>("h03"), _T_665) @[CircuitMath.scala 32:10]
node _T_667 = mux(_T_652, _T_659, _T_666) @[CircuitMath.scala 38:21]
node _T_668 = cat(_T_652, _T_667) @[Cat.scala 30:58]
node _T_669 = bits(_T_646, 7, 4) @[CircuitMath.scala 35:17]
node _T_670 = bits(_T_646, 3, 0) @[CircuitMath.scala 36:17]
node _T_672 = neq(_T_669, UInt<1>("h00")) @[CircuitMath.scala 37:22]
node _T_673 = bits(_T_669, 3, 3) @[CircuitMath.scala 32:12]
node _T_675 = bits(_T_669, 2, 2) @[CircuitMath.scala 32:12]
node _T_677 = bits(_T_669, 1, 1) @[CircuitMath.scala 30:8]
node _T_678 = mux(_T_675, UInt<2>("h02"), _T_677) @[CircuitMath.scala 32:10]
node _T_679 = mux(_T_673, UInt<2>("h03"), _T_678) @[CircuitMath.scala 32:10]
node _T_680 = bits(_T_670, 3, 3) @[CircuitMath.scala 32:12]
node _T_682 = bits(_T_670, 2, 2) @[CircuitMath.scala 32:12]
node _T_684 = bits(_T_670, 1, 1) @[CircuitMath.scala 30:8]
node _T_685 = mux(_T_682, UInt<2>("h02"), _T_684) @[CircuitMath.scala 32:10]
node _T_686 = mux(_T_680, UInt<2>("h03"), _T_685) @[CircuitMath.scala 32:10]
node _T_687 = mux(_T_672, _T_679, _T_686) @[CircuitMath.scala 38:21]
node _T_688 = cat(_T_672, _T_687) @[Cat.scala 30:58]
node _T_689 = mux(_T_648, _T_668, _T_688) @[CircuitMath.scala 38:21]
node _T_690 = cat(_T_648, _T_689) @[Cat.scala 30:58]
node _T_691 = bits(_T_642, 15, 8) @[CircuitMath.scala 35:17]
node _T_692 = bits(_T_642, 7, 0) @[CircuitMath.scala 36:17]
node _T_694 = neq(_T_691, UInt<1>("h00")) @[CircuitMath.scala 37:22]
node _T_695 = bits(_T_691, 7, 4) @[CircuitMath.scala 35:17]
node _T_696 = bits(_T_691, 3, 0) @[CircuitMath.scala 36:17]
node _T_698 = neq(_T_695, UInt<1>("h00")) @[CircuitMath.scala 37:22]
node _T_699 = bits(_T_695, 3, 3) @[CircuitMath.scala 32:12]
node _T_701 = bits(_T_695, 2, 2) @[CircuitMath.scala 32:12]
node _T_703 = bits(_T_695, 1, 1) @[CircuitMath.scala 30:8]
node _T_704 = mux(_T_701, UInt<2>("h02"), _T_703) @[CircuitMath.scala 32:10]
node _T_705 = mux(_T_699, UInt<2>("h03"), _T_704) @[CircuitMath.scala 32:10]
node _T_706 = bits(_T_696, 3, 3) @[CircuitMath.scala 32:12]
node _T_708 = bits(_T_696, 2, 2) @[CircuitMath.scala 32:12]
node _T_710 = bits(_T_696, 1, 1) @[CircuitMath.scala 30:8]
node _T_711 = mux(_T_708, UInt<2>("h02"), _T_710) @[CircuitMath.scala 32:10]
node _T_712 = mux(_T_706, UInt<2>("h03"), _T_711) @[CircuitMath.scala 32:10]
node _T_713 = mux(_T_698, _T_705, _T_712) @[CircuitMath.scala 38:21]
node _T_714 = cat(_T_698, _T_713) @[Cat.scala 30:58]
node _T_715 = bits(_T_692, 7, 4) @[CircuitMath.scala 35:17]
node _T_716 = bits(_T_692, 3, 0) @[CircuitMath.scala 36:17]
node _T_718 = neq(_T_715, UInt<1>("h00")) @[CircuitMath.scala 37:22]
node _T_719 = bits(_T_715, 3, 3) @[CircuitMath.scala 32:12]
node _T_721 = bits(_T_715, 2, 2) @[CircuitMath.scala 32:12]
node _T_723 = bits(_T_715, 1, 1) @[CircuitMath.scala 30:8]
node _T_724 = mux(_T_721, UInt<2>("h02"), _T_723) @[CircuitMath.scala 32:10]
node _T_725 = mux(_T_719, UInt<2>("h03"), _T_724) @[CircuitMath.scala 32:10]
node _T_726 = bits(_T_716, 3, 3) @[CircuitMath.scala 32:12]
node _T_728 = bits(_T_716, 2, 2) @[CircuitMath.scala 32:12]
node _T_730 = bits(_T_716, 1, 1) @[CircuitMath.scala 30:8]
node _T_731 = mux(_T_728, UInt<2>("h02"), _T_730) @[CircuitMath.scala 32:10]
node _T_732 = mux(_T_726, UInt<2>("h03"), _T_731) @[CircuitMath.scala 32:10]
node _T_733 = mux(_T_718, _T_725, _T_732) @[CircuitMath.scala 38:21]
node _T_734 = cat(_T_718, _T_733) @[Cat.scala 30:58]
node _T_735 = mux(_T_694, _T_714, _T_734) @[CircuitMath.scala 38:21]
node _T_736 = cat(_T_694, _T_735) @[Cat.scala 30:58]
node _T_737 = mux(_T_644, _T_690, _T_736) @[CircuitMath.scala 38:21]
node _T_738 = cat(_T_644, _T_737) @[Cat.scala 30:58]
node _T_739 = mux(_T_542, _T_640, _T_738) @[CircuitMath.scala 38:21]
node _T_740 = cat(_T_542, _T_739) @[Cat.scala 30:58]
node _T_741 = not(_T_740) @[recFNFromFN.scala 56:13]
node _T_742 = dshl(_T_532, _T_741) @[recFNFromFN.scala 58:25]
node _T_743 = bits(_T_742, 50, 0) @[recFNFromFN.scala 58:37]
node _T_745 = cat(_T_743, UInt<1>("h00")) @[Cat.scala 30:58]
node _T_750 = mux(UInt<1>("h01"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 71:12]
node _T_751 = xor(_T_741, _T_750) @[recFNFromFN.scala 62:27]
node _T_752 = mux(_T_534, _T_751, _T_531) @[recFNFromFN.scala 61:16]
node _T_756 = mux(_T_534, UInt<2>("h02"), UInt<1>("h01")) @[recFNFromFN.scala 64:47]
node _T_757 = or(UInt<11>("h0400"), _T_756) @[recFNFromFN.scala 64:42]
node _T_758 = add(_T_752, _T_757) @[recFNFromFN.scala 64:15]
node _T_759 = tail(_T_758, 1) @[recFNFromFN.scala 64:15]
node _T_760 = bits(_T_759, 11, 10) @[recFNFromFN.scala 67:25]
node _T_762 = eq(_T_760, UInt<2>("h03")) @[recFNFromFN.scala 67:50]
node _T_764 = eq(_T_536, UInt<1>("h00")) @[recFNFromFN.scala 68:17]
node _T_765 = and(_T_762, _T_764) @[recFNFromFN.scala 67:63]
node _T_766 = bits(_T_537, 0, 0) @[Bitwise.scala 71:15]
node _T_769 = mux(_T_766, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 71:12]
node _T_770 = shl(_T_769, 9) @[recFNFromFN.scala 71:45]
node _T_771 = not(_T_770) @[recFNFromFN.scala 71:28]
node _T_772 = and(_T_759, _T_771) @[recFNFromFN.scala 71:26]
node _T_773 = shl(_T_765, 9) @[recFNFromFN.scala 72:22]
node _T_774 = or(_T_772, _T_773) @[recFNFromFN.scala 71:64]
node _T_775 = mux(_T_534, _T_745, _T_532) @[recFNFromFN.scala 73:27]
node _T_776 = cat(_T_530, _T_774) @[Cat.scala 30:58]
node _T_777 = cat(_T_776, _T_775) @[Cat.scala 30:58]
node _T_779 = or(rec_s, UInt<65>("h0e004000000000000")) @[FPU.scala 543:33]
node load_wb_data_recoded = mux(load_wb_single, _T_779, _T_777) @[FPU.scala 543:10]
cmem regfile : UInt<65>[32] @[FPU.scala 547:20]
when load_wb : @[FPU.scala 548:18]
infer mport _T_782 = regfile[load_wb_tag], clock
_T_782 <= load_wb_data_recoded @[FPU.scala 549:26]
skip @[FPU.scala 548:18]
reg ex_ra1 : UInt, clock @[FPU.scala 554:53]
reg ex_ra2 : UInt, clock @[FPU.scala 554:53]
reg ex_ra3 : UInt, clock @[FPU.scala 554:53]
when io.valid : @[FPU.scala 555:19]
when fp_decoder.io.sigs.ren1 : @[FPU.scala 556:25]
node _T_787 = eq(fp_decoder.io.sigs.swap12, UInt<1>("h00")) @[FPU.scala 557:13]
when _T_787 : @[FPU.scala 557:30]
node _T_788 = bits(io.inst, 19, 15) @[FPU.scala 557:49]
ex_ra1 <= _T_788 @[FPU.scala 557:39]
skip @[FPU.scala 557:30]
when fp_decoder.io.sigs.swap12 : @[FPU.scala 558:29]
node _T_789 = bits(io.inst, 19, 15) @[FPU.scala 558:48]
ex_ra2 <= _T_789 @[FPU.scala 558:38]
skip @[FPU.scala 558:29]
skip @[FPU.scala 556:25]
when fp_decoder.io.sigs.ren2 : @[FPU.scala 560:25]
when fp_decoder.io.sigs.swap12 : @[FPU.scala 561:29]
node _T_790 = bits(io.inst, 24, 20) @[FPU.scala 561:48]
ex_ra1 <= _T_790 @[FPU.scala 561:38]
skip @[FPU.scala 561:29]
when fp_decoder.io.sigs.swap23 : @[FPU.scala 562:29]
node _T_791 = bits(io.inst, 24, 20) @[FPU.scala 562:48]
ex_ra3 <= _T_791 @[FPU.scala 562:38]
skip @[FPU.scala 562:29]
node _T_793 = eq(fp_decoder.io.sigs.swap12, UInt<1>("h00")) @[FPU.scala 563:13]
node _T_795 = eq(fp_decoder.io.sigs.swap23, UInt<1>("h00")) @[FPU.scala 563:32]
node _T_796 = and(_T_793, _T_795) @[FPU.scala 563:29]
when _T_796 : @[FPU.scala 563:49]
node _T_797 = bits(io.inst, 24, 20) @[FPU.scala 563:68]
ex_ra2 <= _T_797 @[FPU.scala 563:58]
skip @[FPU.scala 563:49]
skip @[FPU.scala 560:25]
when fp_decoder.io.sigs.ren3 : @[FPU.scala 565:25]
node _T_798 = bits(io.inst, 31, 27) @[FPU.scala 565:44]
ex_ra3 <= _T_798 @[FPU.scala 565:34]
skip @[FPU.scala 565:25]
skip @[FPU.scala 555:19]
node _T_799 = bits(ex_reg_inst, 14, 12) @[FPU.scala 567:30]
node _T_801 = eq(_T_799, UInt<3>("h07")) @[FPU.scala 567:38]
node _T_802 = bits(ex_reg_inst, 14, 12) @[FPU.scala 567:74]
node ex_rm = mux(_T_801, io.fcsr_rm, _T_802) @[FPU.scala 567:18]
wire req : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} @[FPU.scala 569:17]
req is invalid @[FPU.scala 569:17]
req <- ex_ctrl @[FPU.scala 570:7]
req.rm <= ex_rm @[FPU.scala 571:10]
node _T_847 = or(ex_ra1, UInt<5>("h00"))
node _T_848 = bits(_T_847, 4, 0)
infer mport _T_849 = regfile[_T_848], clock
req.in1 <= _T_849 @[FPU.scala 572:11]
node _T_851 = or(ex_ra2, UInt<5>("h00"))
node _T_852 = bits(_T_851, 4, 0)
infer mport _T_853 = regfile[_T_852], clock
req.in2 <= _T_853 @[FPU.scala 573:11]
node _T_855 = or(ex_ra3, UInt<5>("h00"))
node _T_856 = bits(_T_855, 4, 0)
infer mport _T_857 = regfile[_T_856], clock
req.in3 <= _T_857 @[FPU.scala 574:11]
node _T_858 = bits(ex_reg_inst, 21, 20) @[FPU.scala 575:25]
req.typ <= _T_858 @[FPU.scala 575:11]
when ex_cp_valid : @[FPU.scala 576:22]
req <- io.cp_req.bits @[FPU.scala 577:9]
when io.cp_req.bits.swap23 : @[FPU.scala 578:34]
req.in2 <= io.cp_req.bits.in3 @[FPU.scala 579:15]
req.in3 <= io.cp_req.bits.in2 @[FPU.scala 580:15]
skip @[FPU.scala 578:34]
skip @[FPU.scala 576:22]
inst sfma of FPUFMAPipe @[FPU.scala 584:20]
sfma.io is invalid
sfma.clock <= clock
sfma.reset <= reset
node _T_859 = and(req_valid, ex_ctrl.fma) @[FPU.scala 585:33]
node _T_860 = and(_T_859, ex_ctrl.single) @[FPU.scala 585:48]
sfma.io.in.valid <= _T_860 @[FPU.scala 585:20]
sfma.io.in.bits <- req @[FPU.scala 586:19]
inst fpiu of FPToInt @[FPU.scala 588:20]
fpiu.io is invalid
fpiu.clock <= clock
fpiu.reset <= reset
node _T_861 = or(ex_ctrl.toint, ex_ctrl.div) @[FPU.scala 589:51]
node _T_862 = or(_T_861, ex_ctrl.sqrt) @[FPU.scala 589:66]
node _T_865 = and(ex_ctrl.cmd, UInt<4>("h0d")) @[FPU.scala 589:97]
node _T_866 = eq(UInt<3>("h05"), _T_865) @[FPU.scala 589:97]
node _T_867 = or(_T_862, _T_866) @[FPU.scala 589:82]
node _T_868 = and(req_valid, _T_867) @[FPU.scala 589:33]
fpiu.io.in.valid <= _T_868 @[FPU.scala 589:20]
fpiu.io.in.bits <- req @[FPU.scala 590:19]
io.store_data <= fpiu.io.out.bits.store @[FPU.scala 591:17]
io.toint_data <= fpiu.io.out.bits.toint @[FPU.scala 592:17]
node _T_869 = and(fpiu.io.out.valid, mem_cp_valid) @[FPU.scala 593:26]
node _T_870 = and(_T_869, mem_ctrl.toint) @[FPU.scala 593:42]
when _T_870 : @[FPU.scala 593:60]
io.cp_resp.bits.data <= fpiu.io.out.bits.toint @[FPU.scala 594:26]
io.cp_resp.valid <= UInt<1>("h01") @[FPU.scala 595:22]
skip @[FPU.scala 593:60]
inst ifpu of IntToFP @[FPU.scala 598:20]
ifpu.io is invalid
ifpu.clock <= clock
ifpu.reset <= reset
node _T_872 = and(req_valid, ex_ctrl.fromint) @[FPU.scala 599:33]
ifpu.io.in.valid <= _T_872 @[FPU.scala 599:20]
ifpu.io.in.bits <- req @[FPU.scala 600:19]
node _T_873 = mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) @[FPU.scala 601:29]
ifpu.io.in.bits.in1 <= _T_873 @[FPU.scala 601:23]
inst fpmu of FPToFP @[FPU.scala 603:20]
fpmu.io is invalid
fpmu.clock <= clock
fpmu.reset <= reset
node _T_874 = and(req_valid, ex_ctrl.fastpipe) @[FPU.scala 604:33]
fpmu.io.in.valid <= _T_874 @[FPU.scala 604:20]
fpmu.io.in.bits <- req @[FPU.scala 605:19]
fpmu.io.lt <= fpiu.io.out.bits.lt @[FPU.scala 606:14]
reg divSqrt_wen : UInt<1>, clock @[FPU.scala 608:24]
divSqrt_wen <= UInt<1>("h00") @[FPU.scala 608:24]
wire divSqrt_inReady : UInt<1>
divSqrt_inReady is invalid
divSqrt_inReady <= UInt<1>("h00")
reg divSqrt_waddr : UInt<5>, clock @[FPU.scala 610:26]
reg divSqrt_single : UInt<1>, clock @[FPU.scala 611:27]
wire divSqrt_wdata : UInt<65> @[FPU.scala 612:27]
divSqrt_wdata is invalid @[FPU.scala 612:27]
wire divSqrt_flags : UInt<5> @[FPU.scala 613:27]
divSqrt_flags is invalid @[FPU.scala 613:27]
reg divSqrt_in_flight : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[FPU.scala 614:30]
reg divSqrt_killed : UInt<1>, clock @[FPU.scala 615:27]
inst FPUFMAPipe of FPUFMAPipe_1 @[FPU.scala 624:28]
FPUFMAPipe.io is invalid
FPUFMAPipe.clock <= clock
FPUFMAPipe.reset <= reset
node _T_883 = and(req_valid, ex_ctrl.fma) @[FPU.scala 625:41]
node _T_885 = eq(ex_ctrl.single, UInt<1>("h00")) @[FPU.scala 625:59]
node _T_886 = and(_T_883, _T_885) @[FPU.scala 625:56]
FPUFMAPipe.io.in.valid <= _T_886 @[FPU.scala 625:28]
FPUFMAPipe.io.in.bits <- req @[FPU.scala 626:27]
node _T_889 = mux(mem_ctrl.fastpipe, UInt<1>("h01"), UInt<1>("h00")) @[FPU.scala 631:23]
node _T_892 = mux(mem_ctrl.fromint, UInt<1>("h01"), UInt<1>("h00")) @[FPU.scala 631:23]
node _T_893 = and(mem_ctrl.fma, mem_ctrl.single) @[FPU.scala 622:56]
node _T_896 = mux(_T_893, UInt<2>("h02"), UInt<1>("h00")) @[FPU.scala 631:23]
node _T_898 = eq(mem_ctrl.single, UInt<1>("h00")) @[FPU.scala 627:65]
node _T_899 = and(mem_ctrl.fma, _T_898) @[FPU.scala 627:62]
node _T_902 = mux(_T_899, UInt<3>("h04"), UInt<1>("h00")) @[FPU.scala 631:23]
node _T_903 = or(_T_889, _T_892) @[FPU.scala 631:78]
node _T_904 = or(_T_903, _T_896) @[FPU.scala 631:78]
node memLatencyMask = or(_T_904, _T_902) @[FPU.scala 631:78]
reg wen : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[FPU.scala 645:16]
reg wbInfo : {rd : UInt<5>, single : UInt<1>, cp : UInt<1>, pipeid : UInt<2>}[3], clock @[FPU.scala 646:19]
node _T_966 = or(mem_ctrl.fma, mem_ctrl.fastpipe) @[FPU.scala 647:48]
node _T_967 = or(_T_966, mem_ctrl.fromint) @[FPU.scala 647:69]
node mem_wen = and(mem_reg_valid, _T_967) @[FPU.scala 647:31]
node _T_970 = mux(ex_ctrl.fastpipe, UInt<2>("h02"), UInt<1>("h00")) @[FPU.scala 631:23]
node _T_973 = mux(ex_ctrl.fromint, UInt<2>("h02"), UInt<1>("h00")) @[FPU.scala 631:23]
node _T_974 = and(ex_ctrl.fma, ex_ctrl.single) @[FPU.scala 622:56]
node _T_977 = mux(_T_974, UInt<3>("h04"), UInt<1>("h00")) @[FPU.scala 631:23]
node _T_979 = eq(ex_ctrl.single, UInt<1>("h00")) @[FPU.scala 627:65]
node _T_980 = and(ex_ctrl.fma, _T_979) @[FPU.scala 627:62]
node _T_983 = mux(_T_980, UInt<4>("h08"), UInt<1>("h00")) @[FPU.scala 631:23]
node _T_984 = or(_T_970, _T_973) @[FPU.scala 631:78]
node _T_985 = or(_T_984, _T_977) @[FPU.scala 631:78]
node _T_986 = or(_T_985, _T_983) @[FPU.scala 631:78]
node _T_987 = and(memLatencyMask, _T_986) @[FPU.scala 648:62]
node _T_989 = neq(_T_987, UInt<1>("h00")) @[FPU.scala 648:89]
node _T_990 = and(mem_wen, _T_989) @[FPU.scala 648:43]
node _T_993 = mux(ex_ctrl.fastpipe, UInt<3>("h04"), UInt<1>("h00")) @[FPU.scala 631:23]
node _T_996 = mux(ex_ctrl.fromint, UInt<3>("h04"), UInt<1>("h00")) @[FPU.scala 631:23]
node _T_997 = and(ex_ctrl.fma, ex_ctrl.single) @[FPU.scala 622:56]
node _T_1000 = mux(_T_997, UInt<4>("h08"), UInt<1>("h00")) @[FPU.scala 631:23]
node _T_1002 = eq(ex_ctrl.single, UInt<1>("h00")) @[FPU.scala 627:65]
node _T_1003 = and(ex_ctrl.fma, _T_1002) @[FPU.scala 627:62]
node _T_1006 = mux(_T_1003, UInt<5>("h010"), UInt<1>("h00")) @[FPU.scala 631:23]
node _T_1007 = or(_T_993, _T_996) @[FPU.scala 631:78]
node _T_1008 = or(_T_1007, _T_1000) @[FPU.scala 631:78]
node _T_1009 = or(_T_1008, _T_1006) @[FPU.scala 631:78]
node _T_1010 = and(wen, _T_1009) @[FPU.scala 648:101]
node _T_1012 = neq(_T_1010, UInt<1>("h00")) @[FPU.scala 648:128]
node _T_1013 = or(_T_990, _T_1012) @[FPU.scala 648:93]
reg write_port_busy : UInt<1>, clock @[Reg.scala 34:16]
when req_valid : @[Reg.scala 35:19]
write_port_busy <= _T_1013 @[Reg.scala 35:23]
skip @[Reg.scala 35:19]
node _T_1015 = bits(wen, 1, 1) @[FPU.scala 651:14]
when _T_1015 : @[FPU.scala 651:21]
wbInfo[0] <- wbInfo[1] @[FPU.scala 651:33]
skip @[FPU.scala 651:21]
node _T_1016 = bits(wen, 2, 2) @[FPU.scala 651:14]
when _T_1016 : @[FPU.scala 651:21]
wbInfo[1] <- wbInfo[2] @[FPU.scala 651:33]
skip @[FPU.scala 651:21]
node _T_1017 = shr(wen, 1) @[FPU.scala 653:14]
wen <= _T_1017 @[FPU.scala 653:7]
when mem_wen : @[FPU.scala 654:18]
node _T_1019 = eq(killm, UInt<1>("h00")) @[FPU.scala 655:11]
when _T_1019 : @[FPU.scala 655:19]
node _T_1020 = shr(wen, 1) @[FPU.scala 656:18]
node _T_1021 = or(_T_1020, memLatencyMask) @[FPU.scala 656:23]
wen <= _T_1021 @[FPU.scala 656:11]
skip @[FPU.scala 655:19]
node _T_1023 = eq(write_port_busy, UInt<1>("h00")) @[FPU.scala 659:13]
node _T_1024 = bits(memLatencyMask, 0, 0) @[FPU.scala 659:47]
node _T_1025 = and(_T_1023, _T_1024) @[FPU.scala 659:30]
when _T_1025 : @[FPU.scala 659:52]
wbInfo[0].cp <= mem_cp_valid @[FPU.scala 660:22]
wbInfo[0].single <= mem_ctrl.single @[FPU.scala 661:26]
node _T_1028 = mux(mem_ctrl.fastpipe, UInt<1>("h00"), UInt<1>("h00")) @[FPU.scala 633:63]
node _T_1031 = mux(mem_ctrl.fromint, UInt<1>("h01"), UInt<1>("h00")) @[FPU.scala 633:63]
node _T_1032 = and(mem_ctrl.fma, mem_ctrl.single) @[FPU.scala 622:56]
node _T_1035 = mux(_T_1032, UInt<2>("h02"), UInt<1>("h00")) @[FPU.scala 633:63]
node _T_1037 = eq(mem_ctrl.single, UInt<1>("h00")) @[FPU.scala 627:65]
node _T_1038 = and(mem_ctrl.fma, _T_1037) @[FPU.scala 627:62]
node _T_1041 = mux(_T_1038, UInt<2>("h03"), UInt<1>("h00")) @[FPU.scala 633:63]
node _T_1042 = or(_T_1028, _T_1031) @[FPU.scala 633:108]
node _T_1043 = or(_T_1042, _T_1035) @[FPU.scala 633:108]
node _T_1044 = or(_T_1043, _T_1041) @[FPU.scala 633:108]
wbInfo[0].pipeid <= _T_1044 @[FPU.scala 662:26]
node _T_1045 = bits(mem_reg_inst, 11, 7) @[FPU.scala 663:37]
wbInfo[0].rd <= _T_1045 @[FPU.scala 663:22]
skip @[FPU.scala 659:52]
node _T_1047 = eq(write_port_busy, UInt<1>("h00")) @[FPU.scala 659:13]
node _T_1048 = bits(memLatencyMask, 1, 1) @[FPU.scala 659:47]
node _T_1049 = and(_T_1047, _T_1048) @[FPU.scala 659:30]
when _T_1049 : @[FPU.scala 659:52]
wbInfo[1].cp <= mem_cp_valid @[FPU.scala 660:22]
wbInfo[1].single <= mem_ctrl.single @[FPU.scala 661:26]
node _T_1052 = mux(mem_ctrl.fastpipe, UInt<1>("h00"), UInt<1>("h00")) @[FPU.scala 633:63]
node _T_1055 = mux(mem_ctrl.fromint, UInt<1>("h01"), UInt<1>("h00")) @[FPU.scala 633:63]
node _T_1056 = and(mem_ctrl.fma, mem_ctrl.single) @[FPU.scala 622:56]
node _T_1059 = mux(_T_1056, UInt<2>("h02"), UInt<1>("h00")) @[FPU.scala 633:63]
node _T_1061 = eq(mem_ctrl.single, UInt<1>("h00")) @[FPU.scala 627:65]
node _T_1062 = and(mem_ctrl.fma, _T_1061) @[FPU.scala 627:62]
node _T_1065 = mux(_T_1062, UInt<2>("h03"), UInt<1>("h00")) @[FPU.scala 633:63]
node _T_1066 = or(_T_1052, _T_1055) @[FPU.scala 633:108]
node _T_1067 = or(_T_1066, _T_1059) @[FPU.scala 633:108]
node _T_1068 = or(_T_1067, _T_1065) @[FPU.scala 633:108]
wbInfo[1].pipeid <= _T_1068 @[FPU.scala 662:26]
node _T_1069 = bits(mem_reg_inst, 11, 7) @[FPU.scala 663:37]
wbInfo[1].rd <= _T_1069 @[FPU.scala 663:22]
skip @[FPU.scala 659:52]
node _T_1071 = eq(write_port_busy, UInt<1>("h00")) @[FPU.scala 659:13]
node _T_1072 = bits(memLatencyMask, 2, 2) @[FPU.scala 659:47]
node _T_1073 = and(_T_1071, _T_1072) @[FPU.scala 659:30]
when _T_1073 : @[FPU.scala 659:52]
wbInfo[2].cp <= mem_cp_valid @[FPU.scala 660:22]
wbInfo[2].single <= mem_ctrl.single @[FPU.scala 661:26]
node _T_1076 = mux(mem_ctrl.fastpipe, UInt<1>("h00"), UInt<1>("h00")) @[FPU.scala 633:63]
node _T_1079 = mux(mem_ctrl.fromint, UInt<1>("h01"), UInt<1>("h00")) @[FPU.scala 633:63]
node _T_1080 = and(mem_ctrl.fma, mem_ctrl.single) @[FPU.scala 622:56]
node _T_1083 = mux(_T_1080, UInt<2>("h02"), UInt<1>("h00")) @[FPU.scala 633:63]
node _T_1085 = eq(mem_ctrl.single, UInt<1>("h00")) @[FPU.scala 627:65]
node _T_1086 = and(mem_ctrl.fma, _T_1085) @[FPU.scala 627:62]
node _T_1089 = mux(_T_1086, UInt<2>("h03"), UInt<1>("h00")) @[FPU.scala 633:63]
node _T_1090 = or(_T_1076, _T_1079) @[FPU.scala 633:108]
node _T_1091 = or(_T_1090, _T_1083) @[FPU.scala 633:108]
node _T_1092 = or(_T_1091, _T_1089) @[FPU.scala 633:108]
wbInfo[2].pipeid <= _T_1092 @[FPU.scala 662:26]
node _T_1093 = bits(mem_reg_inst, 11, 7) @[FPU.scala 663:37]
wbInfo[2].rd <= _T_1093 @[FPU.scala 663:22]
skip @[FPU.scala 659:52]
skip @[FPU.scala 654:18]
node waddr = mux(divSqrt_wen, divSqrt_waddr, wbInfo[0].rd) @[FPU.scala 668:18]
node _T_1095 = and(wbInfo[0].pipeid, UInt<1>("h01")) @[Package.scala 18:26]
node _T_1097 = geq(wbInfo[0].pipeid, UInt<2>("h02")) @[Package.scala 19:17]
node _T_1099 = and(_T_1095, UInt<1>("h00")) @[Package.scala 18:26]
node _T_1101 = geq(_T_1095, UInt<1>("h01")) @[Package.scala 19:17]
node _T_1102 = mux(_T_1101, FPUFMAPipe.io.out.bits.data, sfma.io.out.bits.data) @[Package.scala 19:12]
node _T_1104 = and(_T_1095, UInt<1>("h00")) @[Package.scala 18:26]
node _T_1106 = geq(_T_1095, UInt<1>("h01")) @[Package.scala 19:17]
node _T_1107 = mux(_T_1106, ifpu.io.out.bits.data, fpmu.io.out.bits.data) @[Package.scala 19:12]
node _T_1108 = mux(_T_1097, _T_1102, _T_1107) @[Package.scala 19:12]
node wdata0 = mux(divSqrt_wen, divSqrt_wdata, _T_1108) @[FPU.scala 669:19]
node wsingle = mux(divSqrt_wen, divSqrt_single, wbInfo[0].single) @[FPU.scala 670:20]
node _T_1109 = bits(wdata0, 32, 0) @[FPU.scala 673:36]
node _T_1111 = or(_T_1109, UInt<65>("h0e004000000000000")) @[FPU.scala 673:44]
node wdata = mux(wsingle, _T_1111, wdata0) @[FPU.scala 673:19]
node _T_1113 = and(wbInfo[0].pipeid, UInt<1>("h01")) @[Package.scala 18:26]
node _T_1115 = geq(wbInfo[0].pipeid, UInt<2>("h02")) @[Package.scala 19:17]
node _T_1117 = and(_T_1113, UInt<1>("h00")) @[Package.scala 18:26]
node _T_1119 = geq(_T_1113, UInt<1>("h01")) @[Package.scala 19:17]
node _T_1120 = mux(_T_1119, FPUFMAPipe.io.out.bits.exc, sfma.io.out.bits.exc) @[Package.scala 19:12]
node _T_1122 = and(_T_1113, UInt<1>("h00")) @[Package.scala 18:26]
node _T_1124 = geq(_T_1113, UInt<1>("h01")) @[Package.scala 19:17]
node _T_1125 = mux(_T_1124, ifpu.io.out.bits.exc, fpmu.io.out.bits.exc) @[Package.scala 19:12]
node wexc = mux(_T_1115, _T_1120, _T_1125) @[Package.scala 19:12]
node _T_1127 = eq(wbInfo[0].cp, UInt<1>("h00")) @[FPU.scala 676:10]
node _T_1128 = bits(wen, 0, 0) @[FPU.scala 676:30]
node _T_1129 = and(_T_1127, _T_1128) @[FPU.scala 676:24]
node _T_1130 = or(_T_1129, divSqrt_wen) @[FPU.scala 676:35]
when _T_1130 : @[FPU.scala 676:51]
infer mport _T_1131 = regfile[waddr], clock
_T_1131 <= wdata @[FPU.scala 677:20]
skip @[FPU.scala 676:51]
node _T_1132 = bits(wen, 0, 0) @[FPU.scala 689:28]
node _T_1133 = and(wbInfo[0].cp, _T_1132) @[FPU.scala 689:22]
when _T_1133 : @[FPU.scala 689:33]
io.cp_resp.bits.data <= wdata @[FPU.scala 690:26]
io.cp_resp.valid <= UInt<1>("h01") @[FPU.scala 691:22]
skip @[FPU.scala 689:33]
node _T_1136 = eq(ex_reg_valid, UInt<1>("h00")) @[FPU.scala 693:22]
io.cp_req.ready <= _T_1136 @[FPU.scala 693:19]
node wb_toint_valid = and(wb_reg_valid, wb_ctrl.toint) @[FPU.scala 695:37]
reg wb_toint_exc : UInt<5>, clock @[Reg.scala 34:16]
when mem_ctrl.toint : @[Reg.scala 35:19]
wb_toint_exc <= fpiu.io.out.bits.exc @[Reg.scala 35:23]
skip @[Reg.scala 35:19]
node _T_1138 = or(wb_toint_valid, divSqrt_wen) @[FPU.scala 697:41]
node _T_1139 = bits(wen, 0, 0) @[FPU.scala 697:62]
node _T_1140 = or(_T_1138, _T_1139) @[FPU.scala 697:56]
io.fcsr_flags.valid <= _T_1140 @[FPU.scala 697:23]
node _T_1142 = mux(wb_toint_valid, wb_toint_exc, UInt<1>("h00")) @[FPU.scala 699:8]
node _T_1144 = mux(divSqrt_wen, divSqrt_flags, UInt<1>("h00")) @[FPU.scala 700:8]
node _T_1145 = or(_T_1142, _T_1144) @[FPU.scala 699:48]
node _T_1146 = bits(wen, 0, 0) @[FPU.scala 701:12]
node _T_1148 = mux(_T_1146, wexc, UInt<1>("h00")) @[FPU.scala 701:8]
node _T_1149 = or(_T_1145, _T_1148) @[FPU.scala 700:46]
io.fcsr_flags.bits <= _T_1149 @[FPU.scala 698:22]
node _T_1150 = or(mem_ctrl.div, mem_ctrl.sqrt) @[FPU.scala 703:51]
node _T_1151 = and(mem_reg_valid, _T_1150) @[FPU.scala 703:34]
node _T_1153 = eq(divSqrt_inReady, UInt<1>("h00")) @[FPU.scala 703:73]
node _T_1155 = neq(wen, UInt<1>("h00")) @[FPU.scala 703:97]
node _T_1156 = or(_T_1153, _T_1155) @[FPU.scala 703:90]
node units_busy = and(_T_1151, _T_1156) @[FPU.scala 703:69]
node _T_1157 = and(ex_reg_valid, ex_ctrl.wflags) @[FPU.scala 704:33]
node _T_1158 = and(mem_reg_valid, mem_ctrl.wflags) @[FPU.scala 704:68]
node _T_1159 = or(_T_1157, _T_1158) @[FPU.scala 704:51]
node _T_1160 = and(wb_reg_valid, wb_ctrl.toint) @[FPU.scala 704:103]
node _T_1161 = or(_T_1159, _T_1160) @[FPU.scala 704:87]
node _T_1163 = neq(wen, UInt<1>("h00")) @[FPU.scala 704:127]
node _T_1164 = or(_T_1161, _T_1163) @[FPU.scala 704:120]
node _T_1165 = or(_T_1164, divSqrt_in_flight) @[FPU.scala 704:131]
node _T_1167 = eq(_T_1165, UInt<1>("h00")) @[FPU.scala 704:18]
io.fcsr_rdy <= _T_1167 @[FPU.scala 704:15]
node _T_1168 = or(units_busy, write_port_busy) @[FPU.scala 705:29]
node _T_1169 = or(_T_1168, divSqrt_in_flight) @[FPU.scala 705:48]
io.nack_mem <= _T_1169 @[FPU.scala 705:15]
io.dec <- fp_decoder.io.sigs @[FPU.scala 706:10]
node _T_1171 = eq(wb_cp_valid, UInt<1>("h00")) @[FPU.scala 708:36]
node _T_1172 = and(wb_reg_valid, _T_1171) @[FPU.scala 708:33]
node _T_1174 = eq(mem_ctrl.single, UInt<1>("h00")) @[FPU.scala 627:65]
node _T_1175 = and(mem_ctrl.fma, _T_1174) @[FPU.scala 627:62]
node _T_1177 = or(UInt<1>("h00"), _T_1175) @[FPU.scala 707:123]
node _T_1178 = or(_T_1177, mem_ctrl.div) @[FPU.scala 708:96]
node _T_1179 = or(_T_1178, mem_ctrl.sqrt) @[FPU.scala 708:112]
reg _T_1180 : UInt<1>, clock @[FPU.scala 708:55]
_T_1180 <= _T_1179 @[FPU.scala 708:55]
node _T_1181 = and(_T_1172, _T_1180) @[FPU.scala 708:49]
io.sboard_set <= _T_1181 @[FPU.scala 708:17]
node _T_1183 = eq(wb_cp_valid, UInt<1>("h00")) @[FPU.scala 709:20]
node _T_1184 = bits(wen, 0, 0) @[FPU.scala 709:56]
node _T_1186 = eq(wbInfo[0].pipeid, UInt<2>("h03")) @[FPU.scala 709:99]
node _T_1188 = or(UInt<1>("h00"), _T_1186) @[FPU.scala 707:123]
node _T_1189 = and(_T_1184, _T_1188) @[FPU.scala 709:60]
node _T_1190 = or(divSqrt_wen, _T_1189) @[FPU.scala 709:49]
node _T_1191 = and(_T_1183, _T_1190) @[FPU.scala 709:33]
io.sboard_clr <= _T_1191 @[FPU.scala 709:17]
io.sboard_clra <= waddr @[FPU.scala 710:18]
node _T_1192 = bits(io.inst, 14, 14) @[FPU.scala 712:27]
node _T_1193 = bits(io.inst, 13, 12) @[FPU.scala 712:43]
node _T_1195 = lt(_T_1193, UInt<2>("h03")) @[FPU.scala 712:51]
node _T_1197 = geq(io.fcsr_rm, UInt<3>("h04")) @[FPU.scala 712:69]
node _T_1198 = or(_T_1195, _T_1197) @[FPU.scala 712:55]
node _T_1199 = and(_T_1192, _T_1198) @[FPU.scala 712:32]
io.illegal_rm <= _T_1199 @[FPU.scala 712:17]
divSqrt_wdata <= UInt<1>("h00") @[FPU.scala 714:17]
divSqrt_flags <= UInt<1>("h00") @[FPU.scala 715:17]
reg _T_1203 : UInt, clock @[FPU.scala 718:25]
reg _T_1205 : UInt, clock @[FPU.scala 719:35]
reg _T_1207 : UInt, clock @[FPU.scala 720:35]
inst DivSqrtRecF64 of DivSqrtRecF64 @[FPU.scala 722:25]
DivSqrtRecF64.io is invalid
DivSqrtRecF64.clock <= clock
DivSqrtRecF64.reset <= reset
node _T_1208 = mux(DivSqrtRecF64.io.sqrtOp, DivSqrtRecF64.io.inReady_sqrt, DivSqrtRecF64.io.inReady_div) @[FPU.scala 723:27]
divSqrt_inReady <= _T_1208 @[FPU.scala 723:21]
node _T_1209 = or(DivSqrtRecF64.io.outValid_div, DivSqrtRecF64.io.outValid_sqrt) @[FPU.scala 724:52]
node _T_1210 = or(mem_ctrl.div, mem_ctrl.sqrt) @[FPU.scala 725:58]
node _T_1211 = and(mem_reg_valid, _T_1210) @[FPU.scala 725:41]
node _T_1213 = eq(divSqrt_in_flight, UInt<1>("h00")) @[FPU.scala 725:79]
node _T_1214 = and(_T_1211, _T_1213) @[FPU.scala 725:76]
DivSqrtRecF64.io.inValid <= _T_1214 @[FPU.scala 725:24]
DivSqrtRecF64.io.sqrtOp <= mem_ctrl.sqrt @[FPU.scala 726:23]
DivSqrtRecF64.io.a <= fpiu.io.as_double.in1 @[FPU.scala 727:18]
DivSqrtRecF64.io.b <= fpiu.io.as_double.in2 @[FPU.scala 728:18]
DivSqrtRecF64.io.roundingMode <= fpiu.io.as_double.rm @[FPU.scala 729:29]
node _T_1215 = and(DivSqrtRecF64.io.inValid, divSqrt_inReady) @[FPU.scala 731:30]
when _T_1215 : @[FPU.scala 731:50]
divSqrt_in_flight <= UInt<1>("h01") @[FPU.scala 732:25]
divSqrt_killed <= killm @[FPU.scala 733:22]
divSqrt_single <= mem_ctrl.single @[FPU.scala 734:22]
node _T_1217 = bits(mem_reg_inst, 11, 7) @[FPU.scala 735:36]
divSqrt_waddr <= _T_1217 @[FPU.scala 735:21]
_T_1203 <= DivSqrtRecF64.io.roundingMode @[FPU.scala 736:18]
skip @[FPU.scala 731:50]
when _T_1209 : @[FPU.scala 739:29]
node _T_1219 = eq(divSqrt_killed, UInt<1>("h00")) @[FPU.scala 740:22]
divSqrt_wen <= _T_1219 @[FPU.scala 740:19]
_T_1207 <= DivSqrtRecF64.io.out @[FPU.scala 741:28]
divSqrt_in_flight <= UInt<1>("h00") @[FPU.scala 742:25]
_T_1205 <= DivSqrtRecF64.io.exceptionFlags @[FPU.scala 743:28]
skip @[FPU.scala 739:29]
inst RecFNToRecFN of RecFNToRecFN_2 @[FPU.scala 746:34]
RecFNToRecFN.io is invalid
RecFNToRecFN.clock <= clock
RecFNToRecFN.reset <= reset
RecFNToRecFN.io.in <= _T_1207 @[FPU.scala 747:28]
RecFNToRecFN.io.roundingMode <= _T_1203 @[FPU.scala 748:38]
node _T_1221 = mux(divSqrt_single, RecFNToRecFN.io.out, _T_1207) @[FPU.scala 749:25]
divSqrt_wdata <= _T_1221 @[FPU.scala 749:19]
node _T_1223 = mux(divSqrt_single, RecFNToRecFN.io.exceptionFlags, UInt<1>("h00")) @[FPU.scala 750:48]
node _T_1224 = or(_T_1205, _T_1223) @[FPU.scala 750:43]
divSqrt_flags <= _T_1224 @[FPU.scala 750:19]
module FPUDecoder :
input clock : Clock
input reset : UInt<1>
output io : {flip inst : UInt<32>, sigs : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>}}
io is invalid
io is invalid
node _T_22 = and(io.inst, UInt<32>("h04")) @[Decode.scala 13:65]
node _T_24 = eq(_T_22, UInt<32>("h04")) @[Decode.scala 13:121]
node _T_26 = and(io.inst, UInt<32>("h08000010")) @[Decode.scala 13:65]
node _T_28 = eq(_T_26, UInt<32>("h08000010")) @[Decode.scala 13:121]
node _T_30 = or(UInt<1>("h00"), _T_24) @[Decode.scala 14:30]
node _T_31 = or(_T_30, _T_28) @[Decode.scala 14:30]
node _T_33 = and(io.inst, UInt<32>("h08")) @[Decode.scala 13:65]
node _T_35 = eq(_T_33, UInt<32>("h08")) @[Decode.scala 13:121]
node _T_37 = and(io.inst, UInt<32>("h010000010")) @[Decode.scala 13:65]
node _T_39 = eq(_T_37, UInt<32>("h010000010")) @[Decode.scala 13:121]
node _T_41 = or(UInt<1>("h00"), _T_35) @[Decode.scala 14:30]
node _T_42 = or(_T_41, _T_39) @[Decode.scala 14:30]
node _T_44 = and(io.inst, UInt<32>("h040")) @[Decode.scala 13:65]
node _T_46 = eq(_T_44, UInt<32>("h00")) @[Decode.scala 13:121]
node _T_48 = and(io.inst, UInt<32>("h020000000")) @[Decode.scala 13:65]
node _T_50 = eq(_T_48, UInt<32>("h020000000")) @[Decode.scala 13:121]
node _T_52 = or(UInt<1>("h00"), _T_46) @[Decode.scala 14:30]
node _T_53 = or(_T_52, _T_50) @[Decode.scala 14:30]
node _T_55 = and(io.inst, UInt<32>("h040000000")) @[Decode.scala 13:65]
node _T_57 = eq(_T_55, UInt<32>("h040000000")) @[Decode.scala 13:121]
node _T_59 = or(UInt<1>("h00"), _T_46) @[Decode.scala 14:30]
node _T_60 = or(_T_59, _T_57) @[Decode.scala 14:30]
node _T_62 = and(io.inst, UInt<32>("h010")) @[Decode.scala 13:65]
node _T_64 = eq(_T_62, UInt<32>("h00")) @[Decode.scala 13:121]
node _T_66 = or(UInt<1>("h00"), _T_64) @[Decode.scala 14:30]
node _T_67 = cat(_T_42, _T_31) @[Cat.scala 30:58]
node _T_68 = cat(_T_66, _T_60) @[Cat.scala 30:58]
node _T_69 = cat(_T_68, _T_53) @[Cat.scala 30:58]
node decoder_0 = cat(_T_69, _T_67) @[Cat.scala 30:58]
node decoder_1 = or(UInt<1>("h00"), _T_46) @[Decode.scala 14:30]
node _T_72 = and(io.inst, UInt<32>("h080000020")) @[Decode.scala 13:65]
node _T_74 = eq(_T_72, UInt<32>("h00")) @[Decode.scala 13:121]
node _T_76 = and(io.inst, UInt<32>("h030")) @[Decode.scala 13:65]
node _T_78 = eq(_T_76, UInt<32>("h00")) @[Decode.scala 13:121]
node _T_80 = and(io.inst, UInt<32>("h010000020")) @[Decode.scala 13:65]
node _T_82 = eq(_T_80, UInt<32>("h010000000")) @[Decode.scala 13:121]
node _T_84 = or(UInt<1>("h00"), _T_74) @[Decode.scala 14:30]
node _T_85 = or(_T_84, _T_78) @[Decode.scala 14:30]
node decoder_2 = or(_T_85, _T_82) @[Decode.scala 14:30]
node _T_87 = and(io.inst, UInt<32>("h080000004")) @[Decode.scala 13:65]
node _T_89 = eq(_T_87, UInt<32>("h00")) @[Decode.scala 13:121]
node _T_91 = and(io.inst, UInt<32>("h010000004")) @[Decode.scala 13:65]
node _T_93 = eq(_T_91, UInt<32>("h00")) @[Decode.scala 13:121]
node _T_95 = and(io.inst, UInt<32>("h050")) @[Decode.scala 13:65]
node _T_97 = eq(_T_95, UInt<32>("h040")) @[Decode.scala 13:121]
node _T_99 = or(UInt<1>("h00"), _T_89) @[Decode.scala 14:30]
node _T_100 = or(_T_99, _T_93) @[Decode.scala 14:30]
node decoder_3 = or(_T_100, _T_97) @[Decode.scala 14:30]
node _T_102 = and(io.inst, UInt<32>("h040000004")) @[Decode.scala 13:65]
node _T_104 = eq(_T_102, UInt<32>("h00")) @[Decode.scala 13:121]
node _T_106 = and(io.inst, UInt<32>("h020")) @[Decode.scala 13:65]
node _T_108 = eq(_T_106, UInt<32>("h020")) @[Decode.scala 13:121]
node _T_110 = or(UInt<1>("h00"), _T_104) @[Decode.scala 14:30]
node _T_111 = or(_T_110, _T_108) @[Decode.scala 14:30]
node decoder_4 = or(_T_111, _T_97) @[Decode.scala 14:30]
node decoder_5 = or(UInt<1>("h00"), _T_97) @[Decode.scala 14:30]
node _T_114 = and(io.inst, UInt<32>("h050000010")) @[Decode.scala 13:65]
node _T_116 = eq(_T_114, UInt<32>("h050000010")) @[Decode.scala 13:121]
node _T_118 = or(UInt<1>("h00"), _T_46) @[Decode.scala 14:30]
node decoder_6 = or(_T_118, _T_116) @[Decode.scala 14:30]
node _T_120 = and(io.inst, UInt<32>("h030000010")) @[Decode.scala 13:65]
node _T_122 = eq(_T_120, UInt<32>("h010")) @[Decode.scala 13:121]
node decoder_7 = or(UInt<1>("h00"), _T_122) @[Decode.scala 14:30]
node _T_125 = and(io.inst, UInt<32>("h01040")) @[Decode.scala 13:65]
node _T_127 = eq(_T_125, UInt<32>("h00")) @[Decode.scala 13:121]
node _T_129 = and(io.inst, UInt<32>("h02000040")) @[Decode.scala 13:65]
node _T_131 = eq(_T_129, UInt<32>("h040")) @[Decode.scala 13:121]
node _T_133 = or(UInt<1>("h00"), _T_127) @[Decode.scala 14:30]
node decoder_8 = or(_T_133, _T_131) @[Decode.scala 14:30]
node _T_135 = and(io.inst, UInt<32>("h090000010")) @[Decode.scala 13:65]
node _T_137 = eq(_T_135, UInt<32>("h090000010")) @[Decode.scala 13:121]
node decoder_9 = or(UInt<1>("h00"), _T_137) @[Decode.scala 14:30]
node _T_140 = and(io.inst, UInt<32>("h090000010")) @[Decode.scala 13:65]
node _T_142 = eq(_T_140, UInt<32>("h080000010")) @[Decode.scala 13:121]
node _T_144 = or(UInt<1>("h00"), _T_108) @[Decode.scala 14:30]
node decoder_10 = or(_T_144, _T_142) @[Decode.scala 14:30]
node _T_146 = and(io.inst, UInt<32>("h0a0000010")) @[Decode.scala 13:65]
node _T_148 = eq(_T_146, UInt<32>("h020000010")) @[Decode.scala 13:121]
node _T_150 = and(io.inst, UInt<32>("h0d0000010")) @[Decode.scala 13:65]
node _T_152 = eq(_T_150, UInt<32>("h040000010")) @[Decode.scala 13:121]
node _T_154 = or(UInt<1>("h00"), _T_148) @[Decode.scala 14:30]
node decoder_11 = or(_T_154, _T_152) @[Decode.scala 14:30]
node _T_156 = and(io.inst, UInt<32>("h070000004")) @[Decode.scala 13:65]
node _T_158 = eq(_T_156, UInt<32>("h00")) @[Decode.scala 13:121]
node _T_160 = and(io.inst, UInt<32>("h068000004")) @[Decode.scala 13:65]
node _T_162 = eq(_T_160, UInt<32>("h00")) @[Decode.scala 13:121]
node _T_164 = or(UInt<1>("h00"), _T_158) @[Decode.scala 14:30]
node _T_165 = or(_T_164, _T_162) @[Decode.scala 14:30]
node decoder_12 = or(_T_165, _T_97) @[Decode.scala 14:30]
node _T_167 = and(io.inst, UInt<32>("h058000010")) @[Decode.scala 13:65]
node _T_169 = eq(_T_167, UInt<32>("h018000010")) @[Decode.scala 13:121]
node decoder_13 = or(UInt<1>("h00"), _T_169) @[Decode.scala 14:30]
node _T_172 = and(io.inst, UInt<32>("h0d0000010")) @[Decode.scala 13:65]
node _T_174 = eq(_T_172, UInt<32>("h050000010")) @[Decode.scala 13:121]
node decoder_14 = or(UInt<1>("h00"), _T_174) @[Decode.scala 14:30]
node _T_177 = and(io.inst, UInt<32>("h020000004")) @[Decode.scala 13:65]
node _T_179 = eq(_T_177, UInt<32>("h00")) @[Decode.scala 13:121]
node _T_181 = and(io.inst, UInt<32>("h08002000")) @[Decode.scala 13:65]
node _T_183 = eq(_T_181, UInt<32>("h08000000")) @[Decode.scala 13:121]
node _T_185 = and(io.inst, UInt<32>("h0c0000004")) @[Decode.scala 13:65]
node _T_187 = eq(_T_185, UInt<32>("h080000000")) @[Decode.scala 13:121]
node _T_189 = or(UInt<1>("h00"), _T_179) @[Decode.scala 14:30]
node _T_190 = or(_T_189, _T_97) @[Decode.scala 14:30]
node _T_191 = or(_T_190, _T_183) @[Decode.scala 14:30]
node decoder_15 = or(_T_191, _T_187) @[Decode.scala 14:30]
io.sigs.cmd <= decoder_0 @[FPU.scala 149:40]
io.sigs.ldst <= decoder_1 @[FPU.scala 149:40]
io.sigs.wen <= decoder_2 @[FPU.scala 149:40]
io.sigs.ren1 <= decoder_3 @[FPU.scala 149:40]
io.sigs.ren2 <= decoder_4 @[FPU.scala 149:40]
io.sigs.ren3 <= decoder_5 @[FPU.scala 149:40]
io.sigs.swap12 <= decoder_6 @[FPU.scala 149:40]
io.sigs.swap23 <= decoder_7 @[FPU.scala 149:40]
io.sigs.single <= decoder_8 @[FPU.scala 149:40]
io.sigs.fromint <= decoder_9 @[FPU.scala 149:40]
io.sigs.toint <= decoder_10 @[FPU.scala 149:40]
io.sigs.fastpipe <= decoder_11 @[FPU.scala 149:40]
io.sigs.fma <= decoder_12 @[FPU.scala 149:40]
io.sigs.div <= decoder_13 @[FPU.scala 149:40]
io.sigs.sqrt <= decoder_14 @[FPU.scala 149:40]
io.sigs.wflags <= decoder_15 @[FPU.scala 149:40]
module FPUFMAPipe :
input clock : Clock
input reset : UInt<1>
output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}}
io is invalid
io is invalid
node one = shl(UInt<1>("h01"), 31) @[FPU.scala 479:21]
node _T_131 = bits(io.in.bits.in1, 32, 32) @[FPU.scala 480:29]
node _T_132 = bits(io.in.bits.in2, 32, 32) @[FPU.scala 480:53]
node _T_133 = xor(_T_131, _T_132) @[FPU.scala 480:37]
node zero = shl(_T_133, 32) @[FPU.scala 480:62]
reg valid : UInt<1>, clock @[FPU.scala 482:18]
valid <= io.in.valid @[FPU.scala 482:18]
reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock @[FPU.scala 483:15]
when io.in.valid : @[FPU.scala 484:22]
in <- io.in.bits @[FPU.scala 485:8]
node _T_177 = bits(io.in.bits.cmd, 1, 1) @[FPU.scala 488:33]
node _T_178 = or(io.in.bits.ren3, io.in.bits.swap23) @[FPU.scala 488:48]
node _T_179 = and(_T_177, _T_178) @[FPU.scala 488:37]
node _T_180 = bits(io.in.bits.cmd, 0, 0) @[FPU.scala 488:78]
node _T_181 = cat(_T_179, _T_180) @[Cat.scala 30:58]
in.cmd <= _T_181 @[FPU.scala 488:12]
when io.in.bits.swap23 : @[FPU.scala 489:23]
in.in2 <= one @[FPU.scala 489:32]
skip @[FPU.scala 489:23]
node _T_182 = or(io.in.bits.ren3, io.in.bits.swap23) @[FPU.scala 490:21]
node _T_184 = eq(_T_182, UInt<1>("h00")) @[Conditional.scala 19:11]
when _T_184 : @[Conditional.scala 19:15]
in.in3 <= zero @[FPU.scala 490:45]
skip @[Conditional.scala 19:15]
skip @[FPU.scala 484:22]
inst fma of MulAddRecFN @[FPU.scala 493:19]
fma.io is invalid
fma.clock <= clock
fma.reset <= reset
fma.io.op <= in.cmd @[FPU.scala 494:13]
fma.io.roundingMode <= in.rm @[FPU.scala 495:23]
fma.io.a <= in.in1 @[FPU.scala 496:12]
fma.io.b <= in.in2 @[FPU.scala 497:12]
fma.io.c <= in.in3 @[FPU.scala 498:12]
wire res : {data : UInt<65>, exc : UInt<5>} @[FPU.scala 500:17]
res is invalid @[FPU.scala 500:17]
res.data <= fma.io.out @[FPU.scala 501:12]
res.exc <= fma.io.exceptionFlags @[FPU.scala 502:11]
reg _T_192 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Valid.scala 47:18]
_T_192 <= valid @[Valid.scala 47:18]
reg _T_196 : {data : UInt<65>, exc : UInt<5>}, clock @[Reg.scala 34:16]
when valid : @[Reg.scala 35:19]
_T_196 <- res @[Reg.scala 35:23]
skip @[Reg.scala 35:19]
reg _T_201 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Valid.scala 47:18]
_T_201 <= _T_192 @[Valid.scala 47:18]
reg _T_205 : {data : UInt<65>, exc : UInt<5>}, clock @[Reg.scala 34:16]
when _T_192 : @[Reg.scala 35:19]
_T_205 <- _T_196 @[Reg.scala 35:23]
skip @[Reg.scala 35:19]
wire _T_217 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} @[Valid.scala 42:21]
_T_217 is invalid @[Valid.scala 42:21]
_T_217.valid <= _T_201 @[Valid.scala 43:17]
_T_217.bits <- _T_205 @[Valid.scala 44:16]
io.out <- _T_217 @[FPU.scala 503:10]
module FPToInt :
input clock : Clock
input reset : UInt<1>
output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, as_double : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, out : {valid : UInt<1>, bits : {lt : UInt<1>, store : UInt<64>, toint : UInt<64>, exc : UInt<5>}}}
io is invalid
io is invalid
reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock @[FPU.scala 286:15]
reg valid : UInt<1>, clock @[FPU.scala 287:18]
valid <= io.in.valid @[FPU.scala 287:18]
when io.in.valid : @[FPU.scala 291:22]
in <- io.in.bits @[FPU.scala 292:8]
node _T_224 = eq(io.in.bits.ldst, UInt<1>("h00")) @[FPU.scala 293:47]
node _T_225 = and(io.in.bits.single, _T_224) @[FPU.scala 293:44]
node _T_228 = and(io.in.bits.cmd, UInt<4>("h0c")) @[FPU.scala 293:82]
node _T_229 = eq(UInt<4>("h0c"), _T_228) @[FPU.scala 293:82]
node _T_231 = eq(_T_229, UInt<1>("h00")) @[FPU.scala 293:82]
node _T_232 = and(_T_225, _T_231) @[FPU.scala 293:64]
when _T_232 : @[FPU.scala 293:98]
node _T_233 = bits(io.in.bits.in1, 32, 32) @[FPU.scala 237:18]
node _T_234 = bits(io.in.bits.in1, 22, 0) @[FPU.scala 238:21]
node _T_235 = bits(io.in.bits.in1, 31, 23) @[FPU.scala 239:19]
node _T_236 = shl(_T_234, 53) @[FPU.scala 240:28]