Merge pull request #1370 from freechipsproject/misc-fixes

Fix regressions introduced by #1362
chipsalliance · Apr 23, 2018 · 5d7a0e7 · 5d7a0e7
2 parents 1a5559e + e84bddb
commit 5d7a0e7
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Showing 2 changed files with 2 additions and 3 deletions.
diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala
@@ -524,7 +524,6 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
 
   when (insn_wfi && !io.singleStep && !reg_debug) { reg_wfi := true }
   when (pending_interrupts.orR || exception || io.interrupts.debug) { reg_wfi := false }
-  assert(!RegNext(reg_wfi) || io.retire === UInt(0))
 
   when (io.retire(0) || exception) { reg_singleStepped := true }
   when (!io.singleStep) { reg_singleStepped := false }

diff --git a/src/main/scala/rocket/PMP.scala b/src/main/scala/rocket/PMP.scala
@@ -32,8 +32,8 @@ class PMPReg(implicit p: Parameters) extends CoreBundle()(p) {
   val cfg = new PMPConfig
   val addr = UInt(width = paddrBits - PMP.lgAlign)
 
-  def readAddr = {
-    val mask = 1 << (pmpGranularity.log2 - PMP.lgAlign)
+  def readAddr = if (pmpGranularity.log2 == PMP.lgAlign) addr else {
+    val mask = (BigInt(1) << (pmpGranularity.log2 - PMP.lgAlign - 1)).U
     Mux(napot, addr | mask, ~(~addr | mask))
   }
   def napot = cfg.a(1)