HART specific opearations at DRAM controller / adding hartid to memory requests

[FelixWagner00]

Type of issue: other enhancement

Impact: make memory requests separetable by HART at the external memory level

I am currently looking into expanding the memory request operation with the information of which HART is sending it.
The L1d$ accepts memory requests from the rocket core and checks if it is cached. If uncached it sends an acquire message over the TileLink network to the L2$ or directly to the external memory (dependent if L2 cache is to be included or not).
At this point the L2$ only receives an ACQUIRE operation over TileLink which carries Source, Address, Size and a Permission operation.

How exactly is the Source and Address determined?

Is it possible to include the hartid in this acquire message or is it necessary to implement a custom acquire message.
Or is routing the hartid outside of the TileLink network using wires between the components my only option?

Many thanks.