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core-simple.fir
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core-simple.fir
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;buildInfoPackage: chisel3, version: 3.1-SNAPSHOT, scalaVersion: 2.11.7, sbtVersion: 0.13.12, builtAtString: 2018-02-06 00:35:48.108, builtAtMillis: 1517877348108
circuit CoreTester :
module CSR :
input clock : Clock
input reset : UInt<1>
output io : {flip stall : UInt<1>, flip cmd : UInt<3>, flip in : UInt<32>, out : UInt<32>, flip pc : UInt<32>, flip addr : UInt<32>, flip inst : UInt<32>, flip illegal : UInt<1>, flip st_type : UInt<2>, flip ld_type : UInt<3>, flip pc_check : UInt<1>, expt : UInt<1>, evec : UInt<32>, epc : UInt<32>, host : {flip fromhost : {valid : UInt<1>, bits : UInt<32>}, tohost : UInt<32>}}
io is invalid
io is invalid
node csr_addr = bits(io.inst, 31, 20) @[CSR.scala 101:25]
node rs1_addr = bits(io.inst, 19, 15) @[CSR.scala 102:25]
reg time : UInt<32>, clock with : (reset => (reset, UInt<32>("h00"))) @[Reg.scala 26:44]
reg timeh : UInt<32>, clock with : (reset => (reset, UInt<32>("h00"))) @[Reg.scala 26:44]
reg cycle : UInt<32>, clock with : (reset => (reset, UInt<32>("h00"))) @[Reg.scala 26:44]
reg cycleh : UInt<32>, clock with : (reset => (reset, UInt<32>("h00"))) @[Reg.scala 26:44]
reg instret : UInt<32>, clock with : (reset => (reset, UInt<32>("h00"))) @[Reg.scala 26:44]
reg instreth : UInt<32>, clock with : (reset => (reset, UInt<32>("h00"))) @[Reg.scala 26:44]
node _T_53 = cat(UInt<2>("h00"), UInt<4>("h00")) @[Cat.scala 30:58]
node mcpuid = cat(_T_53, UInt<26>("h0100100")) @[Cat.scala 30:58]
reg PRV : UInt<2>, clock with : (reset => (reset, UInt<2>("h03"))) @[Reg.scala 26:44]
reg PRV1 : UInt<2>, clock with : (reset => (reset, UInt<2>("h03"))) @[Reg.scala 26:44]
reg IE : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44]
reg IE1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44]
node _T_93 = cat(IE1, PRV) @[Cat.scala 30:58]
node _T_94 = cat(_T_93, IE) @[Cat.scala 30:58]
node _T_95 = cat(UInt<1>("h00"), PRV1) @[Cat.scala 30:58]
node _T_96 = cat(UInt<1>("h00"), UInt<2>("h00")) @[Cat.scala 30:58]
node _T_97 = cat(_T_96, _T_95) @[Cat.scala 30:58]
node _T_98 = cat(_T_97, _T_94) @[Cat.scala 30:58]
node _T_99 = cat(UInt<2>("h00"), UInt<2>("h00")) @[Cat.scala 30:58]
node _T_100 = cat(_T_99, UInt<2>("h00")) @[Cat.scala 30:58]
node _T_101 = cat(UInt<5>("h00"), UInt<1>("h00")) @[Cat.scala 30:58]
node _T_102 = cat(UInt<1>("h00"), UInt<9>("h00")) @[Cat.scala 30:58]
node _T_103 = cat(_T_102, _T_101) @[Cat.scala 30:58]
node _T_104 = cat(_T_103, _T_100) @[Cat.scala 30:58]
node mstatus = cat(_T_104, _T_98) @[Cat.scala 30:58]
reg MTIP : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44]
reg MTIE : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44]
reg MSIP : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44]
reg MSIE : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 26:44]
node _T_112 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 30:58]
node _T_113 = cat(MSIP, UInt<1>("h00")) @[Cat.scala 30:58]
node _T_114 = cat(_T_113, _T_112) @[Cat.scala 30:58]
node _T_115 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 30:58]
node _T_116 = cat(UInt<24>("h00"), MTIP) @[Cat.scala 30:58]
node _T_117 = cat(_T_116, UInt<1>("h00")) @[Cat.scala 30:58]
node _T_118 = cat(_T_117, _T_115) @[Cat.scala 30:58]
node mip = cat(_T_118, _T_114) @[Cat.scala 30:58]
node _T_122 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 30:58]
node _T_123 = cat(MSIE, UInt<1>("h00")) @[Cat.scala 30:58]
node _T_124 = cat(_T_123, _T_122) @[Cat.scala 30:58]
node _T_125 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 30:58]
node _T_126 = cat(UInt<24>("h00"), MTIE) @[Cat.scala 30:58]
node _T_127 = cat(_T_126, UInt<1>("h00")) @[Cat.scala 30:58]
node _T_128 = cat(_T_127, _T_125) @[Cat.scala 30:58]
node mie = cat(_T_128, _T_124) @[Cat.scala 30:58]
reg mtimecmp : UInt<32>, clock @[CSR.scala 155:21]
reg mscratch : UInt<32>, clock @[CSR.scala 157:21]
reg mepc : UInt<32>, clock @[CSR.scala 159:17]
reg mcause : UInt<32>, clock @[CSR.scala 160:19]
reg mbadaddr : UInt<32>, clock @[CSR.scala 161:21]
reg mtohost : UInt<32>, clock with : (reset => (reset, UInt<32>("h00"))) @[Reg.scala 26:44]
reg mfromhost : UInt<32>, clock @[CSR.scala 164:22]
io.host.tohost <= mtohost @[CSR.scala 165:18]
when io.host.fromhost.valid : @[CSR.scala 166:32]
mfromhost <= io.host.fromhost.bits @[CSR.scala 167:15]
skip @[CSR.scala 166:32]
node _T_139 = and(csr_addr, UInt<12>("h0fff")) @[Lookup.scala 9:38]
node _T_140 = eq(UInt<12>("h0c00"), _T_139) @[Lookup.scala 9:38]
node _T_143 = and(csr_addr, UInt<12>("h0fff")) @[Lookup.scala 9:38]
node _T_144 = eq(UInt<12>("h0c01"), _T_143) @[Lookup.scala 9:38]
node _T_147 = and(csr_addr, UInt<12>("h0fff")) @[Lookup.scala 9:38]
node _T_148 = eq(UInt<12>("h0c02"), _T_147) @[Lookup.scala 9:38]
node _T_151 = and(csr_addr, UInt<12>("h0fff")) @[Lookup.scala 9:38]
node _T_152 = eq(UInt<12>("h0c80"), _T_151) @[Lookup.scala 9:38]
node _T_155 = and(csr_addr, UInt<12>("h0fff")) @[Lookup.scala 9:38]
node _T_156 = eq(UInt<12>("h0c81"), _T_155) @[Lookup.scala 9:38]
node _T_159 = and(csr_addr, UInt<12>("h0fff")) @[Lookup.scala 9:38]
node _T_160 = eq(UInt<12>("h0c82"), _T_159) @[Lookup.scala 9:38]
node _T_163 = and(csr_addr, UInt<12>("h0fff")) @[Lookup.scala 9:38]
node _T_164 = eq(UInt<12>("h0900"), _T_163) @[Lookup.scala 9:38]
node _T_167 = and(csr_addr, UInt<12>("h0fff")) @[Lookup.scala 9:38]
node _T_168 = eq(UInt<12>("h0901"), _T_167) @[Lookup.scala 9:38]
node _T_171 = and(csr_addr, UInt<12>("h0fff")) @[Lookup.scala 9:38]
node _T_172 = eq(UInt<12>("h0902"), _T_171) @[Lookup.scala 9:38]
node _T_175 = and(csr_addr, UInt<12>("h0fff")) @[Lookup.scala 9:38]
node _T_176 = eq(UInt<12>("h0980"), _T_175) @[Lookup.scala 9:38]
node _T_179 = and(csr_addr, UInt<12>("h0fff")) @[Lookup.scala 9:38]
node _T_180 = eq(UInt<12>("h0981"), _T_179) @[Lookup.scala 9:38]
node _T_183 = and(csr_addr, UInt<12>("h0fff")) @[Lookup.scala 9:38]
node _T_184 = eq(UInt<12>("h0982"), _T_183) @[Lookup.scala 9:38]
node _T_187 = and(csr_addr, UInt<12>("h0fff")) @[Lookup.scala 9:38]
node _T_188 = eq(UInt<12>("h0f00"), _T_187) @[Lookup.scala 9:38]
node _T_191 = and(csr_addr, UInt<12>("h0fff")) @[Lookup.scala 9:38]
node _T_192 = eq(UInt<12>("h0f01"), _T_191) @[Lookup.scala 9:38]
node _T_195 = and(csr_addr, UInt<12>("h0fff")) @[Lookup.scala 9:38]
node _T_196 = eq(UInt<12>("h0f10"), _T_195) @[Lookup.scala 9:38]
node _T_199 = and(csr_addr, UInt<12>("h0fff")) @[Lookup.scala 9:38]
node _T_200 = eq(UInt<10>("h0301"), _T_199) @[Lookup.scala 9:38]
node _T_203 = and(csr_addr, UInt<12>("h0fff")) @[Lookup.scala 9:38]
node _T_204 = eq(UInt<10>("h0302"), _T_203) @[Lookup.scala 9:38]
node _T_207 = and(csr_addr, UInt<12>("h0fff")) @[Lookup.scala 9:38]
node _T_208 = eq(UInt<10>("h0304"), _T_207) @[Lookup.scala 9:38]
node _T_211 = and(csr_addr, UInt<12>("h0fff")) @[Lookup.scala 9:38]
node _T_212 = eq(UInt<10>("h0321"), _T_211) @[Lookup.scala 9:38]
node _T_215 = and(csr_addr, UInt<12>("h0fff")) @[Lookup.scala 9:38]
node _T_216 = eq(UInt<11>("h0701"), _T_215) @[Lookup.scala 9:38]
node _T_219 = and(csr_addr, UInt<12>("h0fff")) @[Lookup.scala 9:38]
node _T_220 = eq(UInt<11>("h0741"), _T_219) @[Lookup.scala 9:38]
node _T_223 = and(csr_addr, UInt<12>("h0fff")) @[Lookup.scala 9:38]
node _T_224 = eq(UInt<10>("h0340"), _T_223) @[Lookup.scala 9:38]
node _T_227 = and(csr_addr, UInt<12>("h0fff")) @[Lookup.scala 9:38]
node _T_228 = eq(UInt<10>("h0341"), _T_227) @[Lookup.scala 9:38]
node _T_231 = and(csr_addr, UInt<12>("h0fff")) @[Lookup.scala 9:38]
node _T_232 = eq(UInt<10>("h0342"), _T_231) @[Lookup.scala 9:38]
node _T_235 = and(csr_addr, UInt<12>("h0fff")) @[Lookup.scala 9:38]
node _T_236 = eq(UInt<10>("h0343"), _T_235) @[Lookup.scala 9:38]
node _T_239 = and(csr_addr, UInt<12>("h0fff")) @[Lookup.scala 9:38]
node _T_240 = eq(UInt<10>("h0344"), _T_239) @[Lookup.scala 9:38]
node _T_243 = and(csr_addr, UInt<12>("h0fff")) @[Lookup.scala 9:38]
node _T_244 = eq(UInt<11>("h0780"), _T_243) @[Lookup.scala 9:38]
node _T_247 = and(csr_addr, UInt<12>("h0fff")) @[Lookup.scala 9:38]
node _T_248 = eq(UInt<11>("h0781"), _T_247) @[Lookup.scala 9:38]
node _T_251 = and(csr_addr, UInt<12>("h0fff")) @[Lookup.scala 9:38]
node _T_252 = eq(UInt<10>("h0300"), _T_251) @[Lookup.scala 9:38]
node _T_253 = mux(_T_252, mstatus, UInt<1>("h00")) @[Lookup.scala 11:37]
node _T_254 = mux(_T_248, mfromhost, _T_253) @[Lookup.scala 11:37]
node _T_255 = mux(_T_244, mtohost, _T_254) @[Lookup.scala 11:37]
node _T_256 = mux(_T_240, mip, _T_255) @[Lookup.scala 11:37]
node _T_257 = mux(_T_236, mbadaddr, _T_256) @[Lookup.scala 11:37]
node _T_258 = mux(_T_232, mcause, _T_257) @[Lookup.scala 11:37]
node _T_259 = mux(_T_228, mepc, _T_258) @[Lookup.scala 11:37]
node _T_260 = mux(_T_224, mscratch, _T_259) @[Lookup.scala 11:37]
node _T_261 = mux(_T_220, timeh, _T_260) @[Lookup.scala 11:37]
node _T_262 = mux(_T_216, time, _T_261) @[Lookup.scala 11:37]
node _T_263 = mux(_T_212, mtimecmp, _T_262) @[Lookup.scala 11:37]
node _T_264 = mux(_T_208, mie, _T_263) @[Lookup.scala 11:37]
node _T_265 = mux(_T_204, UInt<32>("h00"), _T_264) @[Lookup.scala 11:37]
node _T_266 = mux(_T_200, UInt<32>("h0100"), _T_265) @[Lookup.scala 11:37]
node _T_267 = mux(_T_196, UInt<32>("h00"), _T_266) @[Lookup.scala 11:37]
node _T_268 = mux(_T_192, UInt<32>("h00"), _T_267) @[Lookup.scala 11:37]
node _T_269 = mux(_T_188, mcpuid, _T_268) @[Lookup.scala 11:37]
node _T_270 = mux(_T_184, instreth, _T_269) @[Lookup.scala 11:37]
node _T_271 = mux(_T_180, timeh, _T_270) @[Lookup.scala 11:37]
node _T_272 = mux(_T_176, cycleh, _T_271) @[Lookup.scala 11:37]
node _T_273 = mux(_T_172, instret, _T_272) @[Lookup.scala 11:37]
node _T_274 = mux(_T_168, time, _T_273) @[Lookup.scala 11:37]
node _T_275 = mux(_T_164, cycle, _T_274) @[Lookup.scala 11:37]
node _T_276 = mux(_T_160, instreth, _T_275) @[Lookup.scala 11:37]
node _T_277 = mux(_T_156, timeh, _T_276) @[Lookup.scala 11:37]
node _T_278 = mux(_T_152, cycleh, _T_277) @[Lookup.scala 11:37]
node _T_279 = mux(_T_148, instret, _T_278) @[Lookup.scala 11:37]
node _T_280 = mux(_T_144, time, _T_279) @[Lookup.scala 11:37]
node _T_281 = mux(_T_140, cycle, _T_280) @[Lookup.scala 11:37]
io.out <= _T_281 @[CSR.scala 202:10]
node _T_282 = bits(csr_addr, 9, 8) @[CSR.scala 204:27]
node privValid = leq(_T_282, PRV) @[CSR.scala 204:34]
node privInst = eq(io.cmd, UInt<3>("h04")) @[CSR.scala 205:26]
node _T_283 = bits(csr_addr, 0, 0) @[CSR.scala 206:40]
node _T_285 = eq(_T_283, UInt<1>("h00")) @[CSR.scala 206:31]
node _T_286 = and(privInst, _T_285) @[CSR.scala 206:28]
node _T_287 = bits(csr_addr, 8, 8) @[CSR.scala 206:56]
node _T_289 = eq(_T_287, UInt<1>("h00")) @[CSR.scala 206:47]
node isEcall = and(_T_286, _T_289) @[CSR.scala 206:44]
node _T_290 = bits(csr_addr, 0, 0) @[CSR.scala 207:40]
node _T_291 = and(privInst, _T_290) @[CSR.scala 207:28]
node _T_292 = bits(csr_addr, 8, 8) @[CSR.scala 207:56]
node _T_294 = eq(_T_292, UInt<1>("h00")) @[CSR.scala 207:47]
node isEbreak = and(_T_291, _T_294) @[CSR.scala 207:44]
node _T_295 = bits(csr_addr, 0, 0) @[CSR.scala 208:40]
node _T_297 = eq(_T_295, UInt<1>("h00")) @[CSR.scala 208:31]
node _T_298 = and(privInst, _T_297) @[CSR.scala 208:28]
node _T_299 = bits(csr_addr, 8, 8) @[CSR.scala 208:56]
node isEret = and(_T_298, _T_299) @[CSR.scala 208:44]
node _T_302 = and(csr_addr, UInt<12>("h0fff")) @[CSR.scala 209:37]
node _T_303 = eq(UInt<12>("h0c00"), _T_302) @[CSR.scala 209:37]
node _T_306 = and(csr_addr, UInt<12>("h0fff")) @[CSR.scala 209:37]
node _T_307 = eq(UInt<12>("h0c01"), _T_306) @[CSR.scala 209:37]
node _T_310 = and(csr_addr, UInt<12>("h0fff")) @[CSR.scala 209:37]
node _T_311 = eq(UInt<12>("h0c02"), _T_310) @[CSR.scala 209:37]
node _T_314 = and(csr_addr, UInt<12>("h0fff")) @[CSR.scala 209:37]
node _T_315 = eq(UInt<12>("h0c80"), _T_314) @[CSR.scala 209:37]
node _T_318 = and(csr_addr, UInt<12>("h0fff")) @[CSR.scala 209:37]
node _T_319 = eq(UInt<12>("h0c81"), _T_318) @[CSR.scala 209:37]
node _T_322 = and(csr_addr, UInt<12>("h0fff")) @[CSR.scala 209:37]
node _T_323 = eq(UInt<12>("h0c82"), _T_322) @[CSR.scala 209:37]
node _T_326 = and(csr_addr, UInt<12>("h0fff")) @[CSR.scala 209:37]
node _T_327 = eq(UInt<12>("h0900"), _T_326) @[CSR.scala 209:37]
node _T_330 = and(csr_addr, UInt<12>("h0fff")) @[CSR.scala 209:37]
node _T_331 = eq(UInt<12>("h0901"), _T_330) @[CSR.scala 209:37]
node _T_334 = and(csr_addr, UInt<12>("h0fff")) @[CSR.scala 209:37]
node _T_335 = eq(UInt<12>("h0902"), _T_334) @[CSR.scala 209:37]
node _T_338 = and(csr_addr, UInt<12>("h0fff")) @[CSR.scala 209:37]
node _T_339 = eq(UInt<12>("h0980"), _T_338) @[CSR.scala 209:37]
node _T_342 = and(csr_addr, UInt<12>("h0fff")) @[CSR.scala 209:37]
node _T_343 = eq(UInt<12>("h0981"), _T_342) @[CSR.scala 209:37]
node _T_346 = and(csr_addr, UInt<12>("h0fff")) @[CSR.scala 209:37]
node _T_347 = eq(UInt<12>("h0982"), _T_346) @[CSR.scala 209:37]
node _T_350 = and(csr_addr, UInt<12>("h0fff")) @[CSR.scala 209:37]
node _T_351 = eq(UInt<12>("h0f00"), _T_350) @[CSR.scala 209:37]
node _T_354 = and(csr_addr, UInt<12>("h0fff")) @[CSR.scala 209:37]
node _T_355 = eq(UInt<12>("h0f01"), _T_354) @[CSR.scala 209:37]
node _T_358 = and(csr_addr, UInt<12>("h0fff")) @[CSR.scala 209:37]
node _T_359 = eq(UInt<12>("h0f10"), _T_358) @[CSR.scala 209:37]
node _T_362 = and(csr_addr, UInt<12>("h0fff")) @[CSR.scala 209:37]
node _T_363 = eq(UInt<10>("h0301"), _T_362) @[CSR.scala 209:37]
node _T_366 = and(csr_addr, UInt<12>("h0fff")) @[CSR.scala 209:37]
node _T_367 = eq(UInt<10>("h0302"), _T_366) @[CSR.scala 209:37]
node _T_370 = and(csr_addr, UInt<12>("h0fff")) @[CSR.scala 209:37]
node _T_371 = eq(UInt<10>("h0304"), _T_370) @[CSR.scala 209:37]
node _T_374 = and(csr_addr, UInt<12>("h0fff")) @[CSR.scala 209:37]
node _T_375 = eq(UInt<10>("h0321"), _T_374) @[CSR.scala 209:37]
node _T_378 = and(csr_addr, UInt<12>("h0fff")) @[CSR.scala 209:37]
node _T_379 = eq(UInt<11>("h0701"), _T_378) @[CSR.scala 209:37]
node _T_382 = and(csr_addr, UInt<12>("h0fff")) @[CSR.scala 209:37]
node _T_383 = eq(UInt<11>("h0741"), _T_382) @[CSR.scala 209:37]
node _T_386 = and(csr_addr, UInt<12>("h0fff")) @[CSR.scala 209:37]
node _T_387 = eq(UInt<10>("h0340"), _T_386) @[CSR.scala 209:37]
node _T_390 = and(csr_addr, UInt<12>("h0fff")) @[CSR.scala 209:37]
node _T_391 = eq(UInt<10>("h0341"), _T_390) @[CSR.scala 209:37]
node _T_394 = and(csr_addr, UInt<12>("h0fff")) @[CSR.scala 209:37]
node _T_395 = eq(UInt<10>("h0342"), _T_394) @[CSR.scala 209:37]
node _T_398 = and(csr_addr, UInt<12>("h0fff")) @[CSR.scala 209:37]
node _T_399 = eq(UInt<10>("h0343"), _T_398) @[CSR.scala 209:37]
node _T_402 = and(csr_addr, UInt<12>("h0fff")) @[CSR.scala 209:37]
node _T_403 = eq(UInt<10>("h0344"), _T_402) @[CSR.scala 209:37]
node _T_406 = and(csr_addr, UInt<12>("h0fff")) @[CSR.scala 209:37]
node _T_407 = eq(UInt<11>("h0780"), _T_406) @[CSR.scala 209:37]
node _T_410 = and(csr_addr, UInt<12>("h0fff")) @[CSR.scala 209:37]
node _T_411 = eq(UInt<11>("h0781"), _T_410) @[CSR.scala 209:37]
node _T_414 = and(csr_addr, UInt<12>("h0fff")) @[CSR.scala 209:37]
node _T_415 = eq(UInt<10>("h0300"), _T_414) @[CSR.scala 209:37]
node _T_416 = or(_T_303, _T_307) @[CSR.scala 209:61]
node _T_417 = or(_T_416, _T_311) @[CSR.scala 209:61]
node _T_418 = or(_T_417, _T_315) @[CSR.scala 209:61]
node _T_419 = or(_T_418, _T_319) @[CSR.scala 209:61]
node _T_420 = or(_T_419, _T_323) @[CSR.scala 209:61]
node _T_421 = or(_T_420, _T_327) @[CSR.scala 209:61]
node _T_422 = or(_T_421, _T_331) @[CSR.scala 209:61]
node _T_423 = or(_T_422, _T_335) @[CSR.scala 209:61]
node _T_424 = or(_T_423, _T_339) @[CSR.scala 209:61]
node _T_425 = or(_T_424, _T_343) @[CSR.scala 209:61]
node _T_426 = or(_T_425, _T_347) @[CSR.scala 209:61]
node _T_427 = or(_T_426, _T_351) @[CSR.scala 209:61]
node _T_428 = or(_T_427, _T_355) @[CSR.scala 209:61]
node _T_429 = or(_T_428, _T_359) @[CSR.scala 209:61]
node _T_430 = or(_T_429, _T_363) @[CSR.scala 209:61]
node _T_431 = or(_T_430, _T_367) @[CSR.scala 209:61]
node _T_432 = or(_T_431, _T_371) @[CSR.scala 209:61]
node _T_433 = or(_T_432, _T_375) @[CSR.scala 209:61]
node _T_434 = or(_T_433, _T_379) @[CSR.scala 209:61]
node _T_435 = or(_T_434, _T_383) @[CSR.scala 209:61]
node _T_436 = or(_T_435, _T_387) @[CSR.scala 209:61]
node _T_437 = or(_T_436, _T_391) @[CSR.scala 209:61]
node _T_438 = or(_T_437, _T_395) @[CSR.scala 209:61]
node _T_439 = or(_T_438, _T_399) @[CSR.scala 209:61]
node _T_440 = or(_T_439, _T_403) @[CSR.scala 209:61]
node _T_441 = or(_T_440, _T_407) @[CSR.scala 209:61]
node _T_442 = or(_T_441, _T_411) @[CSR.scala 209:61]
node csrValid = or(_T_442, _T_415) @[CSR.scala 209:61]
node _T_443 = bits(csr_addr, 11, 10) @[CSR.scala 210:27]
node _T_444 = not(_T_443) @[CSR.scala 210:36]
node _T_446 = eq(_T_444, UInt<1>("h00")) @[CSR.scala 210:36]
node _T_447 = eq(csr_addr, UInt<12>("h0301")) @[CSR.scala 210:53]
node _T_448 = or(_T_446, _T_447) @[CSR.scala 210:41]
node _T_449 = eq(csr_addr, UInt<12>("h0302")) @[CSR.scala 210:79]
node csrRO = or(_T_448, _T_449) @[CSR.scala 210:67]
node _T_450 = eq(io.cmd, UInt<3>("h01")) @[CSR.scala 211:26]
node _T_451 = bits(io.cmd, 1, 1) @[CSR.scala 211:45]
node _T_453 = neq(rs1_addr, UInt<1>("h00")) @[CSR.scala 211:61]
node _T_454 = and(_T_451, _T_453) @[CSR.scala 211:49]
node wen = or(_T_450, _T_454) @[CSR.scala 211:36]
node _T_456 = or(io.out, io.in) @[CSR.scala 214:22]
node _T_457 = not(io.in) @[CSR.scala 215:24]
node _T_458 = and(io.out, _T_457) @[CSR.scala 215:22]
node _T_459 = eq(UInt<3>("h03"), io.cmd) @[Mux.scala 46:19]
node _T_460 = mux(_T_459, _T_458, UInt<1>("h00")) @[Mux.scala 46:16]
node _T_461 = eq(UInt<3>("h02"), io.cmd) @[Mux.scala 46:19]
node _T_462 = mux(_T_461, _T_456, _T_460) @[Mux.scala 46:16]
node _T_463 = eq(UInt<3>("h01"), io.cmd) @[Mux.scala 46:19]
node wdata = mux(_T_463, io.in, _T_462) @[Mux.scala 46:16]
node _T_464 = bits(io.addr, 1, 1) @[CSR.scala 217:44]
node iaddrInvalid = and(io.pc_check, _T_464) @[CSR.scala 217:34]
node _T_519 = bits(io.addr, 1, 0) @[CSR.scala 219:29]
node _T_521 = neq(_T_519, UInt<1>("h00")) @[CSR.scala 219:36]
node _T_522 = bits(io.addr, 0, 0) @[CSR.scala 219:65]
node _T_523 = bits(io.addr, 0, 0) @[CSR.scala 219:95]
node _T_524 = eq(UInt<3>("h04"), io.ld_type) @[Mux.scala 46:19]
node _T_525 = mux(_T_524, _T_523, UInt<1>("h00")) @[Mux.scala 46:16]
node _T_526 = eq(UInt<3>("h02"), io.ld_type) @[Mux.scala 46:19]
node _T_527 = mux(_T_526, _T_522, _T_525) @[Mux.scala 46:16]
node _T_528 = eq(UInt<3>("h01"), io.ld_type) @[Mux.scala 46:19]
node laddrInvalid = mux(_T_528, _T_521, _T_527) @[Mux.scala 46:16]
node _T_530 = bits(io.addr, 1, 0) @[CSR.scala 221:29]
node _T_532 = neq(_T_530, UInt<1>("h00")) @[CSR.scala 221:36]
node _T_533 = bits(io.addr, 0, 0) @[CSR.scala 221:65]
node _T_534 = eq(UInt<2>("h02"), io.st_type) @[Mux.scala 46:19]
node _T_535 = mux(_T_534, _T_533, UInt<1>("h00")) @[Mux.scala 46:16]
node _T_536 = eq(UInt<2>("h01"), io.st_type) @[Mux.scala 46:19]
node saddrInvalid = mux(_T_536, _T_532, _T_535) @[Mux.scala 46:16]
node _T_537 = or(io.illegal, iaddrInvalid) @[CSR.scala 222:25]
node _T_538 = or(_T_537, laddrInvalid) @[CSR.scala 222:41]
node _T_539 = or(_T_538, saddrInvalid) @[CSR.scala 222:57]
node _T_540 = bits(io.cmd, 1, 0) @[CSR.scala 223:20]
node _T_542 = neq(_T_540, UInt<1>("h00")) @[CSR.scala 223:27]
node _T_544 = eq(csrValid, UInt<1>("h00")) @[CSR.scala 223:35]
node _T_546 = eq(privValid, UInt<1>("h00")) @[CSR.scala 223:48]
node _T_547 = or(_T_544, _T_546) @[CSR.scala 223:45]
node _T_548 = and(_T_542, _T_547) @[CSR.scala 223:31]
node _T_549 = or(_T_539, _T_548) @[CSR.scala 222:73]
node _T_550 = and(wen, csrRO) @[CSR.scala 223:67]
node _T_551 = or(_T_549, _T_550) @[CSR.scala 223:60]
node _T_553 = eq(privValid, UInt<1>("h00")) @[CSR.scala 224:27]
node _T_554 = and(privInst, _T_553) @[CSR.scala 224:24]
node _T_555 = or(_T_551, _T_554) @[CSR.scala 223:76]
node _T_556 = or(_T_555, isEcall) @[CSR.scala 224:39]
node _T_557 = or(_T_556, isEbreak) @[CSR.scala 224:50]
io.expt <= _T_557 @[CSR.scala 222:11]
node _T_558 = shl(PRV, 6) @[CSR.scala 225:27]
node _T_559 = add(UInt<32>("h0100"), _T_558) @[CSR.scala 225:20]
node _T_560 = tail(_T_559, 1) @[CSR.scala 225:20]
io.evec <= _T_560 @[CSR.scala 225:11]
io.epc <= mepc @[CSR.scala 226:11]
node _T_562 = add(time, UInt<1>("h01")) @[CSR.scala 229:16]
node _T_563 = tail(_T_562, 1) @[CSR.scala 229:16]
time <= _T_563 @[CSR.scala 229:8]
node _T_564 = not(time) @[CSR.scala 230:13]
node _T_566 = eq(_T_564, UInt<1>("h00")) @[CSR.scala 230:13]
when _T_566 : @[CSR.scala 230:19]
node _T_568 = add(timeh, UInt<1>("h01")) @[CSR.scala 230:36]
node _T_569 = tail(_T_568, 1) @[CSR.scala 230:36]
timeh <= _T_569 @[CSR.scala 230:27]
skip @[CSR.scala 230:19]
node _T_571 = add(cycle, UInt<1>("h01")) @[CSR.scala 231:18]
node _T_572 = tail(_T_571, 1) @[CSR.scala 231:18]
cycle <= _T_572 @[CSR.scala 231:9]
node _T_573 = not(cycle) @[CSR.scala 232:14]
node _T_575 = eq(_T_573, UInt<1>("h00")) @[CSR.scala 232:14]
when _T_575 : @[CSR.scala 232:20]
node _T_577 = add(cycleh, UInt<1>("h01")) @[CSR.scala 232:39]
node _T_578 = tail(_T_577, 1) @[CSR.scala 232:39]
cycleh <= _T_578 @[CSR.scala 232:29]
skip @[CSR.scala 232:20]
node _T_580 = neq(io.inst, UInt<32>("h013")) @[CSR.scala 233:27]
node _T_582 = eq(io.expt, UInt<1>("h00")) @[CSR.scala 233:52]
node _T_583 = or(_T_582, isEcall) @[CSR.scala 233:61]
node _T_584 = or(_T_583, isEbreak) @[CSR.scala 233:72]
node _T_585 = and(_T_580, _T_584) @[CSR.scala 233:48]
node _T_587 = eq(io.stall, UInt<1>("h00")) @[CSR.scala 233:88]
node isInstRet = and(_T_585, _T_587) @[CSR.scala 233:85]
when isInstRet : @[CSR.scala 234:19]
node _T_589 = add(instret, UInt<1>("h01")) @[CSR.scala 234:40]
node _T_590 = tail(_T_589, 1) @[CSR.scala 234:40]
instret <= _T_590 @[CSR.scala 234:29]
skip @[CSR.scala 234:19]
node _T_591 = not(instret) @[CSR.scala 235:29]
node _T_593 = eq(_T_591, UInt<1>("h00")) @[CSR.scala 235:29]
node _T_594 = and(isInstRet, _T_593) @[CSR.scala 235:18]
when _T_594 : @[CSR.scala 235:35]
node _T_596 = add(instreth, UInt<1>("h01")) @[CSR.scala 235:58]
node _T_597 = tail(_T_596, 1) @[CSR.scala 235:58]
instreth <= _T_597 @[CSR.scala 235:46]
skip @[CSR.scala 235:35]
node _T_599 = eq(io.stall, UInt<1>("h00")) @[CSR.scala 237:8]
when _T_599 : @[CSR.scala 237:19]
when io.expt : @[CSR.scala 238:19]
node _T_600 = shr(io.pc, 2) @[CSR.scala 239:23]
node _T_601 = shl(_T_600, 2) @[CSR.scala 239:28]
mepc <= _T_601 @[CSR.scala 239:14]
node _T_608 = add(UInt<4>("h08"), PRV) @[CSR.scala 243:47]
node _T_609 = tail(_T_608, 1) @[CSR.scala 243:47]
node _T_610 = mux(isEbreak, UInt<2>("h03"), UInt<2>("h02")) @[CSR.scala 244:20]
node _T_611 = mux(isEcall, _T_609, _T_610) @[CSR.scala 243:20]
node _T_612 = mux(saddrInvalid, UInt<3>("h06"), _T_611) @[CSR.scala 242:20]
node _T_613 = mux(laddrInvalid, UInt<3>("h04"), _T_612) @[CSR.scala 241:20]
node _T_614 = mux(iaddrInvalid, UInt<1>("h00"), _T_613) @[CSR.scala 240:20]
mcause <= _T_614 @[CSR.scala 240:14]
PRV <= UInt<2>("h03") @[CSR.scala 245:12]
IE <= UInt<1>("h00") @[CSR.scala 246:12]
PRV1 <= PRV @[CSR.scala 247:12]
IE1 <= IE @[CSR.scala 248:12]
node _T_616 = or(iaddrInvalid, laddrInvalid) @[CSR.scala 249:25]
node _T_617 = or(_T_616, saddrInvalid) @[CSR.scala 249:41]
when _T_617 : @[CSR.scala 249:58]
mbadaddr <= io.addr @[CSR.scala 249:69]
skip @[CSR.scala 249:58]
skip @[CSR.scala 238:19]
node _T_619 = eq(io.expt, UInt<1>("h00")) @[CSR.scala 238:19]
node _T_620 = and(_T_619, isEret) @[CSR.scala 250:24]
when _T_620 : @[CSR.scala 250:24]
PRV <= PRV1 @[CSR.scala 251:12]
IE <= IE1 @[CSR.scala 252:12]
PRV1 <= UInt<2>("h00") @[CSR.scala 253:12]
IE1 <= UInt<1>("h01") @[CSR.scala 254:12]
skip @[CSR.scala 250:24]
node _T_623 = eq(io.expt, UInt<1>("h00")) @[CSR.scala 238:19]
node _T_625 = eq(isEret, UInt<1>("h00")) @[CSR.scala 250:24]
node _T_626 = and(_T_623, _T_625) @[CSR.scala 250:24]
node _T_627 = and(_T_626, wen) @[CSR.scala 255:21]
when _T_627 : @[CSR.scala 255:21]
node _T_628 = eq(csr_addr, UInt<12>("h0300")) @[CSR.scala 256:21]
when _T_628 : @[CSR.scala 256:38]
node _T_629 = bits(wdata, 5, 4) @[CSR.scala 257:22]
PRV1 <= _T_629 @[CSR.scala 257:14]
node _T_630 = bits(wdata, 3, 3) @[CSR.scala 258:22]
IE1 <= _T_630 @[CSR.scala 258:14]
node _T_631 = bits(wdata, 2, 1) @[CSR.scala 259:22]
PRV <= _T_631 @[CSR.scala 259:14]
node _T_632 = bits(wdata, 0, 0) @[CSR.scala 260:22]
IE <= _T_632 @[CSR.scala 260:14]
skip @[CSR.scala 256:38]
node _T_633 = eq(csr_addr, UInt<12>("h0344")) @[CSR.scala 262:26]
node _T_635 = eq(_T_628, UInt<1>("h00")) @[CSR.scala 256:38]
node _T_636 = and(_T_635, _T_633) @[CSR.scala 262:39]
when _T_636 : @[CSR.scala 262:39]
node _T_637 = bits(wdata, 7, 7) @[CSR.scala 263:22]
MTIP <= _T_637 @[CSR.scala 263:14]
node _T_638 = bits(wdata, 3, 3) @[CSR.scala 264:22]
MSIP <= _T_638 @[CSR.scala 264:14]
skip @[CSR.scala 262:39]
node _T_639 = eq(csr_addr, UInt<12>("h0304")) @[CSR.scala 266:26]
node _T_641 = eq(_T_628, UInt<1>("h00")) @[CSR.scala 256:38]
node _T_643 = eq(_T_633, UInt<1>("h00")) @[CSR.scala 262:39]
node _T_644 = and(_T_641, _T_643) @[CSR.scala 262:39]
node _T_645 = and(_T_644, _T_639) @[CSR.scala 266:39]
when _T_645 : @[CSR.scala 266:39]
node _T_646 = bits(wdata, 7, 7) @[CSR.scala 267:22]
MTIE <= _T_646 @[CSR.scala 267:14]
node _T_647 = bits(wdata, 3, 3) @[CSR.scala 268:22]
MSIE <= _T_647 @[CSR.scala 268:14]
skip @[CSR.scala 266:39]
node _T_648 = eq(csr_addr, UInt<12>("h0701")) @[CSR.scala 270:26]
node _T_650 = eq(_T_628, UInt<1>("h00")) @[CSR.scala 256:38]
node _T_652 = eq(_T_633, UInt<1>("h00")) @[CSR.scala 262:39]
node _T_653 = and(_T_650, _T_652) @[CSR.scala 262:39]
node _T_655 = eq(_T_639, UInt<1>("h00")) @[CSR.scala 266:39]
node _T_656 = and(_T_653, _T_655) @[CSR.scala 266:39]
node _T_657 = and(_T_656, _T_648) @[CSR.scala 270:41]
when _T_657 : @[CSR.scala 270:41]
time <= wdata @[CSR.scala 270:48]
skip @[CSR.scala 270:41]
node _T_658 = eq(csr_addr, UInt<12>("h0741")) @[CSR.scala 271:26]
node _T_660 = eq(_T_628, UInt<1>("h00")) @[CSR.scala 256:38]
node _T_662 = eq(_T_633, UInt<1>("h00")) @[CSR.scala 262:39]
node _T_663 = and(_T_660, _T_662) @[CSR.scala 262:39]
node _T_665 = eq(_T_639, UInt<1>("h00")) @[CSR.scala 266:39]
node _T_666 = and(_T_663, _T_665) @[CSR.scala 266:39]
node _T_668 = eq(_T_648, UInt<1>("h00")) @[CSR.scala 270:41]
node _T_669 = and(_T_666, _T_668) @[CSR.scala 270:41]
node _T_670 = and(_T_669, _T_658) @[CSR.scala 271:42]
when _T_670 : @[CSR.scala 271:42]
timeh <= wdata @[CSR.scala 271:50]
skip @[CSR.scala 271:42]
node _T_671 = eq(csr_addr, UInt<12>("h0321")) @[CSR.scala 272:26]
node _T_673 = eq(_T_628, UInt<1>("h00")) @[CSR.scala 256:38]
node _T_675 = eq(_T_633, UInt<1>("h00")) @[CSR.scala 262:39]
node _T_676 = and(_T_673, _T_675) @[CSR.scala 262:39]
node _T_678 = eq(_T_639, UInt<1>("h00")) @[CSR.scala 266:39]
node _T_679 = and(_T_676, _T_678) @[CSR.scala 266:39]
node _T_681 = eq(_T_648, UInt<1>("h00")) @[CSR.scala 270:41]
node _T_682 = and(_T_679, _T_681) @[CSR.scala 270:41]
node _T_684 = eq(_T_658, UInt<1>("h00")) @[CSR.scala 271:42]
node _T_685 = and(_T_682, _T_684) @[CSR.scala 271:42]
node _T_686 = and(_T_685, _T_671) @[CSR.scala 272:44]
when _T_686 : @[CSR.scala 272:44]
mtimecmp <= wdata @[CSR.scala 272:55]
skip @[CSR.scala 272:44]
node _T_687 = eq(csr_addr, UInt<12>("h0340")) @[CSR.scala 273:26]
node _T_689 = eq(_T_628, UInt<1>("h00")) @[CSR.scala 256:38]
node _T_691 = eq(_T_633, UInt<1>("h00")) @[CSR.scala 262:39]
node _T_692 = and(_T_689, _T_691) @[CSR.scala 262:39]
node _T_694 = eq(_T_639, UInt<1>("h00")) @[CSR.scala 266:39]
node _T_695 = and(_T_692, _T_694) @[CSR.scala 266:39]
node _T_697 = eq(_T_648, UInt<1>("h00")) @[CSR.scala 270:41]
node _T_698 = and(_T_695, _T_697) @[CSR.scala 270:41]
node _T_700 = eq(_T_658, UInt<1>("h00")) @[CSR.scala 271:42]
node _T_701 = and(_T_698, _T_700) @[CSR.scala 271:42]
node _T_703 = eq(_T_671, UInt<1>("h00")) @[CSR.scala 272:44]
node _T_704 = and(_T_701, _T_703) @[CSR.scala 272:44]
node _T_705 = and(_T_704, _T_687) @[CSR.scala 273:44]
when _T_705 : @[CSR.scala 273:44]
mscratch <= wdata @[CSR.scala 273:55]
skip @[CSR.scala 273:44]
node _T_706 = eq(csr_addr, UInt<12>("h0341")) @[CSR.scala 274:26]
node _T_708 = eq(_T_628, UInt<1>("h00")) @[CSR.scala 256:38]
node _T_710 = eq(_T_633, UInt<1>("h00")) @[CSR.scala 262:39]
node _T_711 = and(_T_708, _T_710) @[CSR.scala 262:39]
node _T_713 = eq(_T_639, UInt<1>("h00")) @[CSR.scala 266:39]
node _T_714 = and(_T_711, _T_713) @[CSR.scala 266:39]
node _T_716 = eq(_T_648, UInt<1>("h00")) @[CSR.scala 270:41]
node _T_717 = and(_T_714, _T_716) @[CSR.scala 270:41]
node _T_719 = eq(_T_658, UInt<1>("h00")) @[CSR.scala 271:42]
node _T_720 = and(_T_717, _T_719) @[CSR.scala 271:42]
node _T_722 = eq(_T_671, UInt<1>("h00")) @[CSR.scala 272:44]
node _T_723 = and(_T_720, _T_722) @[CSR.scala 272:44]
node _T_725 = eq(_T_687, UInt<1>("h00")) @[CSR.scala 273:44]
node _T_726 = and(_T_723, _T_725) @[CSR.scala 273:44]
node _T_727 = and(_T_726, _T_706) @[CSR.scala 274:40]
when _T_727 : @[CSR.scala 274:40]
node _T_729 = dshr(wdata, UInt<2>("h02")) @[CSR.scala 274:56]
node _T_731 = dshl(_T_729, UInt<2>("h02")) @[CSR.scala 274:63]
mepc <= _T_731 @[CSR.scala 274:47]
skip @[CSR.scala 274:40]
node _T_732 = eq(csr_addr, UInt<12>("h0342")) @[CSR.scala 275:26]
node _T_734 = eq(_T_628, UInt<1>("h00")) @[CSR.scala 256:38]
node _T_736 = eq(_T_633, UInt<1>("h00")) @[CSR.scala 262:39]
node _T_737 = and(_T_734, _T_736) @[CSR.scala 262:39]
node _T_739 = eq(_T_639, UInt<1>("h00")) @[CSR.scala 266:39]
node _T_740 = and(_T_737, _T_739) @[CSR.scala 266:39]
node _T_742 = eq(_T_648, UInt<1>("h00")) @[CSR.scala 270:41]
node _T_743 = and(_T_740, _T_742) @[CSR.scala 270:41]
node _T_745 = eq(_T_658, UInt<1>("h00")) @[CSR.scala 271:42]
node _T_746 = and(_T_743, _T_745) @[CSR.scala 271:42]
node _T_748 = eq(_T_671, UInt<1>("h00")) @[CSR.scala 272:44]
node _T_749 = and(_T_746, _T_748) @[CSR.scala 272:44]
node _T_751 = eq(_T_687, UInt<1>("h00")) @[CSR.scala 273:44]
node _T_752 = and(_T_749, _T_751) @[CSR.scala 273:44]
node _T_754 = eq(_T_706, UInt<1>("h00")) @[CSR.scala 274:40]
node _T_755 = and(_T_752, _T_754) @[CSR.scala 274:40]
node _T_756 = and(_T_755, _T_732) @[CSR.scala 275:42]
when _T_756 : @[CSR.scala 275:42]
node _T_758 = and(wdata, UInt<32>("h08000000f")) @[CSR.scala 275:60]
mcause <= _T_758 @[CSR.scala 275:51]
skip @[CSR.scala 275:42]
node _T_759 = eq(csr_addr, UInt<12>("h0343")) @[CSR.scala 276:26]
node _T_761 = eq(_T_628, UInt<1>("h00")) @[CSR.scala 256:38]
node _T_763 = eq(_T_633, UInt<1>("h00")) @[CSR.scala 262:39]
node _T_764 = and(_T_761, _T_763) @[CSR.scala 262:39]
node _T_766 = eq(_T_639, UInt<1>("h00")) @[CSR.scala 266:39]
node _T_767 = and(_T_764, _T_766) @[CSR.scala 266:39]
node _T_769 = eq(_T_648, UInt<1>("h00")) @[CSR.scala 270:41]
node _T_770 = and(_T_767, _T_769) @[CSR.scala 270:41]
node _T_772 = eq(_T_658, UInt<1>("h00")) @[CSR.scala 271:42]
node _T_773 = and(_T_770, _T_772) @[CSR.scala 271:42]
node _T_775 = eq(_T_671, UInt<1>("h00")) @[CSR.scala 272:44]
node _T_776 = and(_T_773, _T_775) @[CSR.scala 272:44]
node _T_778 = eq(_T_687, UInt<1>("h00")) @[CSR.scala 273:44]
node _T_779 = and(_T_776, _T_778) @[CSR.scala 273:44]
node _T_781 = eq(_T_706, UInt<1>("h00")) @[CSR.scala 274:40]
node _T_782 = and(_T_779, _T_781) @[CSR.scala 274:40]
node _T_784 = eq(_T_732, UInt<1>("h00")) @[CSR.scala 275:42]
node _T_785 = and(_T_782, _T_784) @[CSR.scala 275:42]
node _T_786 = and(_T_785, _T_759) @[CSR.scala 276:44]
when _T_786 : @[CSR.scala 276:44]
mbadaddr <= wdata @[CSR.scala 276:55]
skip @[CSR.scala 276:44]
node _T_787 = eq(csr_addr, UInt<12>("h0780")) @[CSR.scala 277:26]
node _T_789 = eq(_T_628, UInt<1>("h00")) @[CSR.scala 256:38]
node _T_791 = eq(_T_633, UInt<1>("h00")) @[CSR.scala 262:39]
node _T_792 = and(_T_789, _T_791) @[CSR.scala 262:39]
node _T_794 = eq(_T_639, UInt<1>("h00")) @[CSR.scala 266:39]
node _T_795 = and(_T_792, _T_794) @[CSR.scala 266:39]
node _T_797 = eq(_T_648, UInt<1>("h00")) @[CSR.scala 270:41]
node _T_798 = and(_T_795, _T_797) @[CSR.scala 270:41]
node _T_800 = eq(_T_658, UInt<1>("h00")) @[CSR.scala 271:42]
node _T_801 = and(_T_798, _T_800) @[CSR.scala 271:42]
node _T_803 = eq(_T_671, UInt<1>("h00")) @[CSR.scala 272:44]
node _T_804 = and(_T_801, _T_803) @[CSR.scala 272:44]
node _T_806 = eq(_T_687, UInt<1>("h00")) @[CSR.scala 273:44]
node _T_807 = and(_T_804, _T_806) @[CSR.scala 273:44]
node _T_809 = eq(_T_706, UInt<1>("h00")) @[CSR.scala 274:40]
node _T_810 = and(_T_807, _T_809) @[CSR.scala 274:40]
node _T_812 = eq(_T_732, UInt<1>("h00")) @[CSR.scala 275:42]
node _T_813 = and(_T_810, _T_812) @[CSR.scala 275:42]
node _T_815 = eq(_T_759, UInt<1>("h00")) @[CSR.scala 276:44]
node _T_816 = and(_T_813, _T_815) @[CSR.scala 276:44]
node _T_817 = and(_T_816, _T_787) @[CSR.scala 277:43]
when _T_817 : @[CSR.scala 277:43]
mtohost <= wdata @[CSR.scala 277:53]
skip @[CSR.scala 277:43]
node _T_818 = eq(csr_addr, UInt<12>("h0781")) @[CSR.scala 278:26]
node _T_820 = eq(_T_628, UInt<1>("h00")) @[CSR.scala 256:38]
node _T_822 = eq(_T_633, UInt<1>("h00")) @[CSR.scala 262:39]
node _T_823 = and(_T_820, _T_822) @[CSR.scala 262:39]
node _T_825 = eq(_T_639, UInt<1>("h00")) @[CSR.scala 266:39]
node _T_826 = and(_T_823, _T_825) @[CSR.scala 266:39]
node _T_828 = eq(_T_648, UInt<1>("h00")) @[CSR.scala 270:41]
node _T_829 = and(_T_826, _T_828) @[CSR.scala 270:41]
node _T_831 = eq(_T_658, UInt<1>("h00")) @[CSR.scala 271:42]
node _T_832 = and(_T_829, _T_831) @[CSR.scala 271:42]
node _T_834 = eq(_T_671, UInt<1>("h00")) @[CSR.scala 272:44]
node _T_835 = and(_T_832, _T_834) @[CSR.scala 272:44]
node _T_837 = eq(_T_687, UInt<1>("h00")) @[CSR.scala 273:44]
node _T_838 = and(_T_835, _T_837) @[CSR.scala 273:44]
node _T_840 = eq(_T_706, UInt<1>("h00")) @[CSR.scala 274:40]
node _T_841 = and(_T_838, _T_840) @[CSR.scala 274:40]
node _T_843 = eq(_T_732, UInt<1>("h00")) @[CSR.scala 275:42]
node _T_844 = and(_T_841, _T_843) @[CSR.scala 275:42]
node _T_846 = eq(_T_759, UInt<1>("h00")) @[CSR.scala 276:44]
node _T_847 = and(_T_844, _T_846) @[CSR.scala 276:44]
node _T_849 = eq(_T_787, UInt<1>("h00")) @[CSR.scala 277:43]
node _T_850 = and(_T_847, _T_849) @[CSR.scala 277:43]
node _T_851 = and(_T_850, _T_818) @[CSR.scala 278:45]
when _T_851 : @[CSR.scala 278:45]
mfromhost <= wdata @[CSR.scala 278:57]
skip @[CSR.scala 278:45]
node _T_852 = eq(csr_addr, UInt<12>("h0900")) @[CSR.scala 279:26]
node _T_854 = eq(_T_628, UInt<1>("h00")) @[CSR.scala 256:38]
node _T_856 = eq(_T_633, UInt<1>("h00")) @[CSR.scala 262:39]
node _T_857 = and(_T_854, _T_856) @[CSR.scala 262:39]
node _T_859 = eq(_T_639, UInt<1>("h00")) @[CSR.scala 266:39]
node _T_860 = and(_T_857, _T_859) @[CSR.scala 266:39]
node _T_862 = eq(_T_648, UInt<1>("h00")) @[CSR.scala 270:41]
node _T_863 = and(_T_860, _T_862) @[CSR.scala 270:41]
node _T_865 = eq(_T_658, UInt<1>("h00")) @[CSR.scala 271:42]
node _T_866 = and(_T_863, _T_865) @[CSR.scala 271:42]
node _T_868 = eq(_T_671, UInt<1>("h00")) @[CSR.scala 272:44]
node _T_869 = and(_T_866, _T_868) @[CSR.scala 272:44]
node _T_871 = eq(_T_687, UInt<1>("h00")) @[CSR.scala 273:44]
node _T_872 = and(_T_869, _T_871) @[CSR.scala 273:44]
node _T_874 = eq(_T_706, UInt<1>("h00")) @[CSR.scala 274:40]
node _T_875 = and(_T_872, _T_874) @[CSR.scala 274:40]
node _T_877 = eq(_T_732, UInt<1>("h00")) @[CSR.scala 275:42]
node _T_878 = and(_T_875, _T_877) @[CSR.scala 275:42]
node _T_880 = eq(_T_759, UInt<1>("h00")) @[CSR.scala 276:44]
node _T_881 = and(_T_878, _T_880) @[CSR.scala 276:44]
node _T_883 = eq(_T_787, UInt<1>("h00")) @[CSR.scala 277:43]
node _T_884 = and(_T_881, _T_883) @[CSR.scala 277:43]
node _T_886 = eq(_T_818, UInt<1>("h00")) @[CSR.scala 278:45]
node _T_887 = and(_T_884, _T_886) @[CSR.scala 278:45]
node _T_888 = and(_T_887, _T_852) @[CSR.scala 279:42]
when _T_888 : @[CSR.scala 279:42]
cycle <= wdata @[CSR.scala 279:50]
skip @[CSR.scala 279:42]
node _T_889 = eq(csr_addr, UInt<12>("h0901")) @[CSR.scala 280:26]
node _T_891 = eq(_T_628, UInt<1>("h00")) @[CSR.scala 256:38]
node _T_893 = eq(_T_633, UInt<1>("h00")) @[CSR.scala 262:39]
node _T_894 = and(_T_891, _T_893) @[CSR.scala 262:39]
node _T_896 = eq(_T_639, UInt<1>("h00")) @[CSR.scala 266:39]
node _T_897 = and(_T_894, _T_896) @[CSR.scala 266:39]
node _T_899 = eq(_T_648, UInt<1>("h00")) @[CSR.scala 270:41]
node _T_900 = and(_T_897, _T_899) @[CSR.scala 270:41]
node _T_902 = eq(_T_658, UInt<1>("h00")) @[CSR.scala 271:42]
node _T_903 = and(_T_900, _T_902) @[CSR.scala 271:42]
node _T_905 = eq(_T_671, UInt<1>("h00")) @[CSR.scala 272:44]
node _T_906 = and(_T_903, _T_905) @[CSR.scala 272:44]
node _T_908 = eq(_T_687, UInt<1>("h00")) @[CSR.scala 273:44]
node _T_909 = and(_T_906, _T_908) @[CSR.scala 273:44]
node _T_911 = eq(_T_706, UInt<1>("h00")) @[CSR.scala 274:40]
node _T_912 = and(_T_909, _T_911) @[CSR.scala 274:40]
node _T_914 = eq(_T_732, UInt<1>("h00")) @[CSR.scala 275:42]
node _T_915 = and(_T_912, _T_914) @[CSR.scala 275:42]
node _T_917 = eq(_T_759, UInt<1>("h00")) @[CSR.scala 276:44]
node _T_918 = and(_T_915, _T_917) @[CSR.scala 276:44]
node _T_920 = eq(_T_787, UInt<1>("h00")) @[CSR.scala 277:43]
node _T_921 = and(_T_918, _T_920) @[CSR.scala 277:43]
node _T_923 = eq(_T_818, UInt<1>("h00")) @[CSR.scala 278:45]
node _T_924 = and(_T_921, _T_923) @[CSR.scala 278:45]
node _T_926 = eq(_T_852, UInt<1>("h00")) @[CSR.scala 279:42]
node _T_927 = and(_T_924, _T_926) @[CSR.scala 279:42]
node _T_928 = and(_T_927, _T_889) @[CSR.scala 280:41]
when _T_928 : @[CSR.scala 280:41]
time <= wdata @[CSR.scala 280:48]
skip @[CSR.scala 280:41]
node _T_929 = eq(csr_addr, UInt<12>("h0902")) @[CSR.scala 281:26]
node _T_931 = eq(_T_628, UInt<1>("h00")) @[CSR.scala 256:38]
node _T_933 = eq(_T_633, UInt<1>("h00")) @[CSR.scala 262:39]
node _T_934 = and(_T_931, _T_933) @[CSR.scala 262:39]
node _T_936 = eq(_T_639, UInt<1>("h00")) @[CSR.scala 266:39]
node _T_937 = and(_T_934, _T_936) @[CSR.scala 266:39]
node _T_939 = eq(_T_648, UInt<1>("h00")) @[CSR.scala 270:41]
node _T_940 = and(_T_937, _T_939) @[CSR.scala 270:41]
node _T_942 = eq(_T_658, UInt<1>("h00")) @[CSR.scala 271:42]
node _T_943 = and(_T_940, _T_942) @[CSR.scala 271:42]
node _T_945 = eq(_T_671, UInt<1>("h00")) @[CSR.scala 272:44]
node _T_946 = and(_T_943, _T_945) @[CSR.scala 272:44]
node _T_948 = eq(_T_687, UInt<1>("h00")) @[CSR.scala 273:44]
node _T_949 = and(_T_946, _T_948) @[CSR.scala 273:44]
node _T_951 = eq(_T_706, UInt<1>("h00")) @[CSR.scala 274:40]
node _T_952 = and(_T_949, _T_951) @[CSR.scala 274:40]
node _T_954 = eq(_T_732, UInt<1>("h00")) @[CSR.scala 275:42]
node _T_955 = and(_T_952, _T_954) @[CSR.scala 275:42]
node _T_957 = eq(_T_759, UInt<1>("h00")) @[CSR.scala 276:44]
node _T_958 = and(_T_955, _T_957) @[CSR.scala 276:44]
node _T_960 = eq(_T_787, UInt<1>("h00")) @[CSR.scala 277:43]
node _T_961 = and(_T_958, _T_960) @[CSR.scala 277:43]
node _T_963 = eq(_T_818, UInt<1>("h00")) @[CSR.scala 278:45]
node _T_964 = and(_T_961, _T_963) @[CSR.scala 278:45]
node _T_966 = eq(_T_852, UInt<1>("h00")) @[CSR.scala 279:42]
node _T_967 = and(_T_964, _T_966) @[CSR.scala 279:42]
node _T_969 = eq(_T_889, UInt<1>("h00")) @[CSR.scala 280:41]
node _T_970 = and(_T_967, _T_969) @[CSR.scala 280:41]
node _T_971 = and(_T_970, _T_929) @[CSR.scala 281:44]
when _T_971 : @[CSR.scala 281:44]
instret <= wdata @[CSR.scala 281:54]
skip @[CSR.scala 281:44]
node _T_972 = eq(csr_addr, UInt<12>("h0980")) @[CSR.scala 282:26]
node _T_974 = eq(_T_628, UInt<1>("h00")) @[CSR.scala 256:38]
node _T_976 = eq(_T_633, UInt<1>("h00")) @[CSR.scala 262:39]
node _T_977 = and(_T_974, _T_976) @[CSR.scala 262:39]
node _T_979 = eq(_T_639, UInt<1>("h00")) @[CSR.scala 266:39]
node _T_980 = and(_T_977, _T_979) @[CSR.scala 266:39]
node _T_982 = eq(_T_648, UInt<1>("h00")) @[CSR.scala 270:41]
node _T_983 = and(_T_980, _T_982) @[CSR.scala 270:41]
node _T_985 = eq(_T_658, UInt<1>("h00")) @[CSR.scala 271:42]
node _T_986 = and(_T_983, _T_985) @[CSR.scala 271:42]
node _T_988 = eq(_T_671, UInt<1>("h00")) @[CSR.scala 272:44]
node _T_989 = and(_T_986, _T_988) @[CSR.scala 272:44]
node _T_991 = eq(_T_687, UInt<1>("h00")) @[CSR.scala 273:44]
node _T_992 = and(_T_989, _T_991) @[CSR.scala 273:44]
node _T_994 = eq(_T_706, UInt<1>("h00")) @[CSR.scala 274:40]
node _T_995 = and(_T_992, _T_994) @[CSR.scala 274:40]
node _T_997 = eq(_T_732, UInt<1>("h00")) @[CSR.scala 275:42]
node _T_998 = and(_T_995, _T_997) @[CSR.scala 275:42]
node _T_1000 = eq(_T_759, UInt<1>("h00")) @[CSR.scala 276:44]
node _T_1001 = and(_T_998, _T_1000) @[CSR.scala 276:44]
node _T_1003 = eq(_T_787, UInt<1>("h00")) @[CSR.scala 277:43]
node _T_1004 = and(_T_1001, _T_1003) @[CSR.scala 277:43]
node _T_1006 = eq(_T_818, UInt<1>("h00")) @[CSR.scala 278:45]
node _T_1007 = and(_T_1004, _T_1006) @[CSR.scala 278:45]
node _T_1009 = eq(_T_852, UInt<1>("h00")) @[CSR.scala 279:42]
node _T_1010 = and(_T_1007, _T_1009) @[CSR.scala 279:42]
node _T_1012 = eq(_T_889, UInt<1>("h00")) @[CSR.scala 280:41]
node _T_1013 = and(_T_1010, _T_1012) @[CSR.scala 280:41]
node _T_1015 = eq(_T_929, UInt<1>("h00")) @[CSR.scala 281:44]
node _T_1016 = and(_T_1013, _T_1015) @[CSR.scala 281:44]
node _T_1017 = and(_T_1016, _T_972) @[CSR.scala 282:43]
when _T_1017 : @[CSR.scala 282:43]
cycleh <= wdata @[CSR.scala 282:52]
skip @[CSR.scala 282:43]
node _T_1018 = eq(csr_addr, UInt<12>("h0981")) @[CSR.scala 283:26]
node _T_1020 = eq(_T_628, UInt<1>("h00")) @[CSR.scala 256:38]
node _T_1022 = eq(_T_633, UInt<1>("h00")) @[CSR.scala 262:39]
node _T_1023 = and(_T_1020, _T_1022) @[CSR.scala 262:39]
node _T_1025 = eq(_T_639, UInt<1>("h00")) @[CSR.scala 266:39]
node _T_1026 = and(_T_1023, _T_1025) @[CSR.scala 266:39]
node _T_1028 = eq(_T_648, UInt<1>("h00")) @[CSR.scala 270:41]
node _T_1029 = and(_T_1026, _T_1028) @[CSR.scala 270:41]
node _T_1031 = eq(_T_658, UInt<1>("h00")) @[CSR.scala 271:42]
node _T_1032 = and(_T_1029, _T_1031) @[CSR.scala 271:42]
node _T_1034 = eq(_T_671, UInt<1>("h00")) @[CSR.scala 272:44]
node _T_1035 = and(_T_1032, _T_1034) @[CSR.scala 272:44]
node _T_1037 = eq(_T_687, UInt<1>("h00")) @[CSR.scala 273:44]
node _T_1038 = and(_T_1035, _T_1037) @[CSR.scala 273:44]
node _T_1040 = eq(_T_706, UInt<1>("h00")) @[CSR.scala 274:40]
node _T_1041 = and(_T_1038, _T_1040) @[CSR.scala 274:40]
node _T_1043 = eq(_T_732, UInt<1>("h00")) @[CSR.scala 275:42]
node _T_1044 = and(_T_1041, _T_1043) @[CSR.scala 275:42]
node _T_1046 = eq(_T_759, UInt<1>("h00")) @[CSR.scala 276:44]
node _T_1047 = and(_T_1044, _T_1046) @[CSR.scala 276:44]
node _T_1049 = eq(_T_787, UInt<1>("h00")) @[CSR.scala 277:43]
node _T_1050 = and(_T_1047, _T_1049) @[CSR.scala 277:43]
node _T_1052 = eq(_T_818, UInt<1>("h00")) @[CSR.scala 278:45]
node _T_1053 = and(_T_1050, _T_1052) @[CSR.scala 278:45]
node _T_1055 = eq(_T_852, UInt<1>("h00")) @[CSR.scala 279:42]
node _T_1056 = and(_T_1053, _T_1055) @[CSR.scala 279:42]
node _T_1058 = eq(_T_889, UInt<1>("h00")) @[CSR.scala 280:41]
node _T_1059 = and(_T_1056, _T_1058) @[CSR.scala 280:41]
node _T_1061 = eq(_T_929, UInt<1>("h00")) @[CSR.scala 281:44]
node _T_1062 = and(_T_1059, _T_1061) @[CSR.scala 281:44]
node _T_1064 = eq(_T_972, UInt<1>("h00")) @[CSR.scala 282:43]
node _T_1065 = and(_T_1062, _T_1064) @[CSR.scala 282:43]
node _T_1066 = and(_T_1065, _T_1018) @[CSR.scala 283:42]
when _T_1066 : @[CSR.scala 283:42]
timeh <= wdata @[CSR.scala 283:50]
skip @[CSR.scala 283:42]
node _T_1067 = eq(csr_addr, UInt<12>("h0982")) @[CSR.scala 284:26]
node _T_1069 = eq(_T_628, UInt<1>("h00")) @[CSR.scala 256:38]
node _T_1071 = eq(_T_633, UInt<1>("h00")) @[CSR.scala 262:39]
node _T_1072 = and(_T_1069, _T_1071) @[CSR.scala 262:39]
node _T_1074 = eq(_T_639, UInt<1>("h00")) @[CSR.scala 266:39]
node _T_1075 = and(_T_1072, _T_1074) @[CSR.scala 266:39]
node _T_1077 = eq(_T_648, UInt<1>("h00")) @[CSR.scala 270:41]
node _T_1078 = and(_T_1075, _T_1077) @[CSR.scala 270:41]
node _T_1080 = eq(_T_658, UInt<1>("h00")) @[CSR.scala 271:42]
node _T_1081 = and(_T_1078, _T_1080) @[CSR.scala 271:42]
node _T_1083 = eq(_T_671, UInt<1>("h00")) @[CSR.scala 272:44]
node _T_1084 = and(_T_1081, _T_1083) @[CSR.scala 272:44]
node _T_1086 = eq(_T_687, UInt<1>("h00")) @[CSR.scala 273:44]
node _T_1087 = and(_T_1084, _T_1086) @[CSR.scala 273:44]
node _T_1089 = eq(_T_706, UInt<1>("h00")) @[CSR.scala 274:40]
node _T_1090 = and(_T_1087, _T_1089) @[CSR.scala 274:40]
node _T_1092 = eq(_T_732, UInt<1>("h00")) @[CSR.scala 275:42]
node _T_1093 = and(_T_1090, _T_1092) @[CSR.scala 275:42]
node _T_1095 = eq(_T_759, UInt<1>("h00")) @[CSR.scala 276:44]
node _T_1096 = and(_T_1093, _T_1095) @[CSR.scala 276:44]
node _T_1098 = eq(_T_787, UInt<1>("h00")) @[CSR.scala 277:43]
node _T_1099 = and(_T_1096, _T_1098) @[CSR.scala 277:43]
node _T_1101 = eq(_T_818, UInt<1>("h00")) @[CSR.scala 278:45]
node _T_1102 = and(_T_1099, _T_1101) @[CSR.scala 278:45]
node _T_1104 = eq(_T_852, UInt<1>("h00")) @[CSR.scala 279:42]
node _T_1105 = and(_T_1102, _T_1104) @[CSR.scala 279:42]
node _T_1107 = eq(_T_889, UInt<1>("h00")) @[CSR.scala 280:41]
node _T_1108 = and(_T_1105, _T_1107) @[CSR.scala 280:41]
node _T_1110 = eq(_T_929, UInt<1>("h00")) @[CSR.scala 281:44]
node _T_1111 = and(_T_1108, _T_1110) @[CSR.scala 281:44]
node _T_1113 = eq(_T_972, UInt<1>("h00")) @[CSR.scala 282:43]
node _T_1114 = and(_T_1111, _T_1113) @[CSR.scala 282:43]
node _T_1116 = eq(_T_1018, UInt<1>("h00")) @[CSR.scala 283:42]
node _T_1117 = and(_T_1114, _T_1116) @[CSR.scala 283:42]
node _T_1118 = and(_T_1117, _T_1067) @[CSR.scala 284:45]
when _T_1118 : @[CSR.scala 284:45]
instreth <= wdata @[CSR.scala 284:56]
skip @[CSR.scala 284:45]
skip @[CSR.scala 255:21]
skip @[CSR.scala 237:19]
module RegFile :
input clock : Clock
input reset : UInt<1>
output io : {flip raddr1 : UInt<5>, flip raddr2 : UInt<5>, rdata1 : UInt<32>, rdata2 : UInt<32>, flip wen : UInt<1>, flip waddr : UInt<5>, flip wdata : UInt<32>}
io is invalid
io is invalid
cmem regs : UInt<32>[32] @[RegFile.scala 20:17]
node _T_19 = neq(io.raddr1, UInt<1>("h00")) @[RegFile.scala 21:30]
infer mport _T_20 = regs[io.raddr1], clock
node _T_22 = mux(_T_19, _T_20, UInt<1>("h00")) @[RegFile.scala 21:19]
io.rdata1 <= _T_22 @[RegFile.scala 21:13]
node _T_24 = neq(io.raddr2, UInt<1>("h00")) @[RegFile.scala 22:30]
infer mport _T_25 = regs[io.raddr2], clock
node _T_27 = mux(_T_24, _T_25, UInt<1>("h00")) @[RegFile.scala 22:19]
io.rdata2 <= _T_27 @[RegFile.scala 22:13]
node _T_29 = neq(io.waddr, UInt<1>("h00")) @[RegFile.scala 23:26]
node _T_30 = and(io.wen, _T_29) @[RegFile.scala 23:15]
when _T_30 : @[RegFile.scala 23:31]
infer mport _T_31 = regs[io.waddr], clock
_T_31 <= io.wdata @[RegFile.scala 24:20]
skip @[RegFile.scala 23:31]
module ALUArea :
input clock : Clock
input reset : UInt<1>
output io : {flip A : UInt<32>, flip B : UInt<32>, flip alu_op : UInt<4>, out : UInt<32>, sum : UInt<32>}
io is invalid
io is invalid
node _T_12 = bits(io.alu_op, 0, 0) @[ALU.scala 59:33]
node _T_14 = sub(UInt<1>("h00"), io.B) @[ALU.scala 59:38]
node _T_15 = tail(_T_14, 1) @[ALU.scala 59:38]
node _T_16 = mux(_T_12, _T_15, io.B) @[ALU.scala 59:23]
node _T_17 = add(io.A, _T_16) @[ALU.scala 59:18]
node sum = tail(_T_17, 1) @[ALU.scala 59:18]
node _T_18 = bits(io.A, 31, 31) @[ALU.scala 60:21]
node _T_19 = bits(io.B, 31, 31) @[ALU.scala 60:38]
node _T_20 = eq(_T_18, _T_19) @[ALU.scala 60:30]
node _T_21 = bits(sum, 31, 31) @[ALU.scala 60:51]
node _T_22 = bits(io.alu_op, 1, 1) @[ALU.scala 61:26]
node _T_23 = bits(io.B, 31, 31) @[ALU.scala 61:35]
node _T_24 = bits(io.A, 31, 31) @[ALU.scala 61:49]
node _T_25 = mux(_T_22, _T_23, _T_24) @[ALU.scala 61:16]
node cmp = mux(_T_20, _T_21, _T_25) @[ALU.scala 60:16]
node shamt = bits(io.B, 4, 0) @[ALU.scala 62:20]
node _T_26 = bits(io.alu_op, 3, 3) @[ALU.scala 63:29]
node _T_29 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 101:47]
node _T_30 = xor(UInt<32>("h0ffffffff"), _T_29) @[Bitwise.scala 101:21]
node _T_31 = shr(io.A, 16) @[Bitwise.scala 102:21]
node _T_32 = and(_T_31, _T_30) @[Bitwise.scala 102:31]
node _T_33 = bits(io.A, 15, 0) @[Bitwise.scala 102:46]
node _T_34 = shl(_T_33, 16) @[Bitwise.scala 102:65]
node _T_35 = not(_T_30) @[Bitwise.scala 102:77]
node _T_36 = and(_T_34, _T_35) @[Bitwise.scala 102:75]
node _T_37 = or(_T_32, _T_36) @[Bitwise.scala 102:39]
node _T_38 = bits(_T_30, 23, 0) @[Bitwise.scala 101:28]
node _T_39 = shl(_T_38, 8) @[Bitwise.scala 101:47]
node _T_40 = xor(_T_30, _T_39) @[Bitwise.scala 101:21]
node _T_41 = shr(_T_37, 8) @[Bitwise.scala 102:21]
node _T_42 = and(_T_41, _T_40) @[Bitwise.scala 102:31]
node _T_43 = bits(_T_37, 23, 0) @[Bitwise.scala 102:46]
node _T_44 = shl(_T_43, 8) @[Bitwise.scala 102:65]
node _T_45 = not(_T_40) @[Bitwise.scala 102:77]
node _T_46 = and(_T_44, _T_45) @[Bitwise.scala 102:75]
node _T_47 = or(_T_42, _T_46) @[Bitwise.scala 102:39]
node _T_48 = bits(_T_40, 27, 0) @[Bitwise.scala 101:28]
node _T_49 = shl(_T_48, 4) @[Bitwise.scala 101:47]
node _T_50 = xor(_T_40, _T_49) @[Bitwise.scala 101:21]
node _T_51 = shr(_T_47, 4) @[Bitwise.scala 102:21]
node _T_52 = and(_T_51, _T_50) @[Bitwise.scala 102:31]
node _T_53 = bits(_T_47, 27, 0) @[Bitwise.scala 102:46]
node _T_54 = shl(_T_53, 4) @[Bitwise.scala 102:65]
node _T_55 = not(_T_50) @[Bitwise.scala 102:77]
node _T_56 = and(_T_54, _T_55) @[Bitwise.scala 102:75]
node _T_57 = or(_T_52, _T_56) @[Bitwise.scala 102:39]
node _T_58 = bits(_T_50, 29, 0) @[Bitwise.scala 101:28]
node _T_59 = shl(_T_58, 2) @[Bitwise.scala 101:47]
node _T_60 = xor(_T_50, _T_59) @[Bitwise.scala 101:21]
node _T_61 = shr(_T_57, 2) @[Bitwise.scala 102:21]
node _T_62 = and(_T_61, _T_60) @[Bitwise.scala 102:31]
node _T_63 = bits(_T_57, 29, 0) @[Bitwise.scala 102:46]
node _T_64 = shl(_T_63, 2) @[Bitwise.scala 102:65]
node _T_65 = not(_T_60) @[Bitwise.scala 102:77]
node _T_66 = and(_T_64, _T_65) @[Bitwise.scala 102:75]
node _T_67 = or(_T_62, _T_66) @[Bitwise.scala 102:39]
node _T_68 = bits(_T_60, 30, 0) @[Bitwise.scala 101:28]
node _T_69 = shl(_T_68, 1) @[Bitwise.scala 101:47]
node _T_70 = xor(_T_60, _T_69) @[Bitwise.scala 101:21]
node _T_71 = shr(_T_67, 1) @[Bitwise.scala 102:21]
node _T_72 = and(_T_71, _T_70) @[Bitwise.scala 102:31]
node _T_73 = bits(_T_67, 30, 0) @[Bitwise.scala 102:46]
node _T_74 = shl(_T_73, 1) @[Bitwise.scala 102:65]
node _T_75 = not(_T_70) @[Bitwise.scala 102:77]
node _T_76 = and(_T_74, _T_75) @[Bitwise.scala 102:75]
node _T_77 = or(_T_72, _T_76) @[Bitwise.scala 102:39]
node shin = mux(_T_26, io.A, _T_77) @[ALU.scala 63:19]
node _T_78 = bits(io.alu_op, 0, 0) @[ALU.scala 64:30]
node _T_79 = bits(shin, 31, 31) @[ALU.scala 64:41]
node _T_80 = and(_T_78, _T_79) @[ALU.scala 64:34]
node _T_81 = cat(_T_80, shin) @[Cat.scala 30:58]
node _T_82 = asSInt(_T_81) @[ALU.scala 64:57]
node _T_83 = dshr(_T_82, shamt) @[ALU.scala 64:64]
node shiftr = bits(_T_83, 31, 0) @[ALU.scala 64:73]
node _T_86 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 101:47]
node _T_87 = xor(UInt<32>("h0ffffffff"), _T_86) @[Bitwise.scala 101:21]
node _T_88 = shr(shiftr, 16) @[Bitwise.scala 102:21]
node _T_89 = and(_T_88, _T_87) @[Bitwise.scala 102:31]
node _T_90 = bits(shiftr, 15, 0) @[Bitwise.scala 102:46]
node _T_91 = shl(_T_90, 16) @[Bitwise.scala 102:65]
node _T_92 = not(_T_87) @[Bitwise.scala 102:77]
node _T_93 = and(_T_91, _T_92) @[Bitwise.scala 102:75]
node _T_94 = or(_T_89, _T_93) @[Bitwise.scala 102:39]
node _T_95 = bits(_T_87, 23, 0) @[Bitwise.scala 101:28]
node _T_96 = shl(_T_95, 8) @[Bitwise.scala 101:47]
node _T_97 = xor(_T_87, _T_96) @[Bitwise.scala 101:21]
node _T_98 = shr(_T_94, 8) @[Bitwise.scala 102:21]
node _T_99 = and(_T_98, _T_97) @[Bitwise.scala 102:31]
node _T_100 = bits(_T_94, 23, 0) @[Bitwise.scala 102:46]
node _T_101 = shl(_T_100, 8) @[Bitwise.scala 102:65]
node _T_102 = not(_T_97) @[Bitwise.scala 102:77]
node _T_103 = and(_T_101, _T_102) @[Bitwise.scala 102:75]
node _T_104 = or(_T_99, _T_103) @[Bitwise.scala 102:39]
node _T_105 = bits(_T_97, 27, 0) @[Bitwise.scala 101:28]
node _T_106 = shl(_T_105, 4) @[Bitwise.scala 101:47]
node _T_107 = xor(_T_97, _T_106) @[Bitwise.scala 101:21]
node _T_108 = shr(_T_104, 4) @[Bitwise.scala 102:21]
node _T_109 = and(_T_108, _T_107) @[Bitwise.scala 102:31]
node _T_110 = bits(_T_104, 27, 0) @[Bitwise.scala 102:46]
node _T_111 = shl(_T_110, 4) @[Bitwise.scala 102:65]
node _T_112 = not(_T_107) @[Bitwise.scala 102:77]
node _T_113 = and(_T_111, _T_112) @[Bitwise.scala 102:75]
node _T_114 = or(_T_109, _T_113) @[Bitwise.scala 102:39]
node _T_115 = bits(_T_107, 29, 0) @[Bitwise.scala 101:28]
node _T_116 = shl(_T_115, 2) @[Bitwise.scala 101:47]
node _T_117 = xor(_T_107, _T_116) @[Bitwise.scala 101:21]
node _T_118 = shr(_T_114, 2) @[Bitwise.scala 102:21]
node _T_119 = and(_T_118, _T_117) @[Bitwise.scala 102:31]
node _T_120 = bits(_T_114, 29, 0) @[Bitwise.scala 102:46]
node _T_121 = shl(_T_120, 2) @[Bitwise.scala 102:65]
node _T_122 = not(_T_117) @[Bitwise.scala 102:77]
node _T_123 = and(_T_121, _T_122) @[Bitwise.scala 102:75]
node _T_124 = or(_T_119, _T_123) @[Bitwise.scala 102:39]
node _T_125 = bits(_T_117, 30, 0) @[Bitwise.scala 101:28]
node _T_126 = shl(_T_125, 1) @[Bitwise.scala 101:47]
node _T_127 = xor(_T_117, _T_126) @[Bitwise.scala 101:21]
node _T_128 = shr(_T_124, 1) @[Bitwise.scala 102:21]
node _T_129 = and(_T_128, _T_127) @[Bitwise.scala 102:31]
node _T_130 = bits(_T_124, 30, 0) @[Bitwise.scala 102:46]
node _T_131 = shl(_T_130, 1) @[Bitwise.scala 102:65]
node _T_132 = not(_T_127) @[Bitwise.scala 102:77]
node _T_133 = and(_T_131, _T_132) @[Bitwise.scala 102:75]
node shiftl = or(_T_129, _T_133) @[Bitwise.scala 102:39]
node _T_134 = eq(io.alu_op, UInt<4>("h00")) @[ALU.scala 68:19]
node _T_135 = eq(io.alu_op, UInt<4>("h01")) @[ALU.scala 68:44]
node _T_136 = or(_T_134, _T_135) @[ALU.scala 68:31]
node _T_137 = eq(io.alu_op, UInt<4>("h05")) @[ALU.scala 69:19]
node _T_138 = eq(io.alu_op, UInt<4>("h07")) @[ALU.scala 69:44]
node _T_139 = or(_T_137, _T_138) @[ALU.scala 69:31]
node _T_140 = eq(io.alu_op, UInt<4>("h09")) @[ALU.scala 70:19]
node _T_141 = eq(io.alu_op, UInt<4>("h08")) @[ALU.scala 70:44]
node _T_142 = or(_T_140, _T_141) @[ALU.scala 70:31]
node _T_143 = eq(io.alu_op, UInt<4>("h06")) @[ALU.scala 71:19]
node _T_144 = eq(io.alu_op, UInt<4>("h02")) @[ALU.scala 72:19]
node _T_145 = and(io.A, io.B) @[ALU.scala 72:38]
node _T_146 = eq(io.alu_op, UInt<4>("h03")) @[ALU.scala 73:19]
node _T_147 = or(io.A, io.B) @[ALU.scala 73:38]
node _T_148 = eq(io.alu_op, UInt<4>("h04")) @[ALU.scala 74:19]
node _T_149 = xor(io.A, io.B) @[ALU.scala 74:38]
node _T_150 = eq(io.alu_op, UInt<4>("h0a")) @[ALU.scala 75:19]
node _T_151 = mux(_T_150, io.A, io.B) @[ALU.scala 75:8]
node _T_152 = mux(_T_148, _T_149, _T_151) @[ALU.scala 74:8]
node _T_153 = mux(_T_146, _T_147, _T_152) @[ALU.scala 73:8]
node _T_154 = mux(_T_144, _T_145, _T_153) @[ALU.scala 72:8]
node _T_155 = mux(_T_143, shiftl, _T_154) @[ALU.scala 71:8]
node _T_156 = mux(_T_142, shiftr, _T_155) @[ALU.scala 70:8]
node _T_157 = shl(cmp, 0) @[ALU.scala 69:8]
node _T_158 = mux(_T_139, _T_157, _T_156) @[ALU.scala 69:8]
node out = mux(_T_136, sum, _T_158) @[ALU.scala 68:8]
io.out <= out @[ALU.scala 78:10]
io.sum <= sum @[ALU.scala 79:10]
module ImmGenWire :
input clock : Clock
input reset : UInt<1>
output io : {flip inst : UInt<32>, flip sel : UInt<3>, out : UInt<32>}
io is invalid
io is invalid
node _T_8 = bits(io.inst, 31, 20) @[ImmGen.scala 21:21]
node Iimm = asSInt(_T_8) @[ImmGen.scala 21:30]
node _T_9 = bits(io.inst, 31, 25) @[ImmGen.scala 22:25]
node _T_10 = bits(io.inst, 11, 7) @[ImmGen.scala 22:42]
node _T_11 = cat(_T_9, _T_10) @[Cat.scala 30:58]
node Simm = asSInt(_T_11) @[ImmGen.scala 22:50]
node _T_12 = bits(io.inst, 31, 31) @[ImmGen.scala 23:25]
node _T_13 = bits(io.inst, 7, 7) @[ImmGen.scala 23:38]
node _T_14 = bits(io.inst, 30, 25) @[ImmGen.scala 23:50]
node _T_15 = bits(io.inst, 11, 8) @[ImmGen.scala 23:67]
node _T_17 = cat(_T_15, UInt<1>("h00")) @[Cat.scala 30:58]
node _T_18 = cat(_T_12, _T_13) @[Cat.scala 30:58]
node _T_19 = cat(_T_18, _T_14) @[Cat.scala 30:58]
node _T_20 = cat(_T_19, _T_17) @[Cat.scala 30:58]