test1.vcd

$version Generated by VerilatedVcd $end
$date Sat Dec 14 21:02:18 2019
 $end
$timescale   1ns $end

 $scope module TOP $end
  $var wire  1 & clock $end
  $var wire  1 ' reset $end
  $var wire  5 $ wire1 [4:0] $end
  $var wire  5 % wire2 [4:0] $end
 $upscope $end
$enddefinitions $end


#0
1&
b00001 $
b00010 %
#1
0&
b00011 $
b00100 %
#2
1&
b00101 $
b00110 %