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Rob.fir
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Rob.fir
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circuit Rob :
module Rob :
input clk : Clock
input reset : UInt<1>
output io : {flip dis_valids : UInt<1>[2], flip dis_uops : {valid : UInt<1>, iw_state : UInt<2>, uopc : UInt<9>, inst : UInt<32>, pc : UInt<40>, fu_code : UInt<8>, ctrl : {br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<4>, fcn_dw : UInt<1>, rf_wen : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, wakeup_delay : UInt<2>, allocate_brtag : UInt<1>, is_br_or_jmp : UInt<1>, is_jump : UInt<1>, is_jal : UInt<1>, is_ret : UInt<1>, is_call : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, br_prediction : {bpd_predict_val : UInt<1>, bpd_predict_taken : UInt<1>, btb_hit : UInt<1>, btb_predicted : UInt<1>, is_br_or_jalr : UInt<1>}, stat_brjmp_mispredicted : UInt<1>, stat_btb_made_pred : UInt<1>, stat_btb_mispredicted : UInt<1>, stat_bpd_made_pred : UInt<1>, stat_bpd_mispredicted : UInt<1>, fetch_pc_lob : UInt<3>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, brob_idx : UInt<5>, pdst : UInt<7>, pop1 : UInt<7>, pop2 : UInt<7>, pop3 : UInt<7>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<4>, mem_typ : UInt<3>, is_fence : UInt<1>, is_fencei : UInt<1>, is_store : UInt<1>, is_amo : UInt<1>, is_load : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_if : UInt<1>, replay_if : UInt<1>, debug_wdata : UInt<64>, debug_events : {fetch_seq : UInt<32>}}[2], flip dis_has_br_or_jalr_in_packet : UInt<1>, flip dis_partial_stall : UInt<1>, flip dis_new_packet : UInt<1>, curr_rob_tail : UInt<6>, flip wb_resps : {valid : UInt<1>, bits : {uop : {valid : UInt<1>, iw_state : UInt<2>, uopc : UInt<9>, inst : UInt<32>, pc : UInt<40>, fu_code : UInt<8>, ctrl : {br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<4>, fcn_dw : UInt<1>, rf_wen : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, wakeup_delay : UInt<2>, allocate_brtag : UInt<1>, is_br_or_jmp : UInt<1>, is_jump : UInt<1>, is_jal : UInt<1>, is_ret : UInt<1>, is_call : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, br_prediction : {bpd_predict_val : UInt<1>, bpd_predict_taken : UInt<1>, btb_hit : UInt<1>, btb_predicted : UInt<1>, is_br_or_jalr : UInt<1>}, stat_brjmp_mispredicted : UInt<1>, stat_btb_made_pred : UInt<1>, stat_btb_mispredicted : UInt<1>, stat_bpd_made_pred : UInt<1>, stat_bpd_mispredicted : UInt<1>, fetch_pc_lob : UInt<3>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, brob_idx : UInt<5>, pdst : UInt<7>, pop1 : UInt<7>, pop2 : UInt<7>, pop3 : UInt<7>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<4>, mem_typ : UInt<3>, is_fence : UInt<1>, is_fencei : UInt<1>, is_store : UInt<1>, is_amo : UInt<1>, is_load : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_if : UInt<1>, replay_if : UInt<1>, debug_wdata : UInt<64>, debug_events : {fetch_seq : UInt<32>}}, data : UInt<65>, fflags : {valid : UInt<1>, bits : {uop : {valid : UInt<1>, iw_state : UInt<2>, uopc : UInt<9>, inst : UInt<32>, pc : UInt<40>, fu_code : UInt<8>, ctrl : {br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<4>, fcn_dw : UInt<1>, rf_wen : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, wakeup_delay : UInt<2>, allocate_brtag : UInt<1>, is_br_or_jmp : UInt<1>, is_jump : UInt<1>, is_jal : UInt<1>, is_ret : UInt<1>, is_call : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, br_prediction : {bpd_predict_val : UInt<1>, bpd_predict_taken : UInt<1>, btb_hit : UInt<1>, btb_predicted : UInt<1>, is_br_or_jalr : UInt<1>}, stat_brjmp_mispredicted : UInt<1>, stat_btb_made_pred : UInt<1>, stat_btb_mispredicted : UInt<1>, stat_bpd_made_pred : UInt<1>, stat_bpd_mispredicted : UInt<1>, fetch_pc_lob : UInt<3>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, brob_idx : UInt<5>, pdst : UInt<7>, pop1 : UInt<7>, pop2 : UInt<7>, pop3 : UInt<7>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<4>, mem_typ : UInt<3>, is_fence : UInt<1>, is_fencei : UInt<1>, is_store : UInt<1>, is_amo : UInt<1>, is_load : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_if : UInt<1>, replay_if : UInt<1>, debug_wdata : UInt<64>, debug_events : {fetch_seq : UInt<32>}}, flags : UInt<5>}}}}[3], flip debug_wb_valids : UInt<1>[3], flip debug_wb_wdata : UInt<64>[3], flip fflags : {valid : UInt<1>, bits : {uop : {valid : UInt<1>, iw_state : UInt<2>, uopc : UInt<9>, inst : UInt<32>, pc : UInt<40>, fu_code : UInt<8>, ctrl : {br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<4>, fcn_dw : UInt<1>, rf_wen : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, wakeup_delay : UInt<2>, allocate_brtag : UInt<1>, is_br_or_jmp : UInt<1>, is_jump : UInt<1>, is_jal : UInt<1>, is_ret : UInt<1>, is_call : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, br_prediction : {bpd_predict_val : UInt<1>, bpd_predict_taken : UInt<1>, btb_hit : UInt<1>, btb_predicted : UInt<1>, is_br_or_jalr : UInt<1>}, stat_brjmp_mispredicted : UInt<1>, stat_btb_made_pred : UInt<1>, stat_btb_mispredicted : UInt<1>, stat_bpd_made_pred : UInt<1>, stat_bpd_mispredicted : UInt<1>, fetch_pc_lob : UInt<3>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, brob_idx : UInt<5>, pdst : UInt<7>, pop1 : UInt<7>, pop2 : UInt<7>, pop3 : UInt<7>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<4>, mem_typ : UInt<3>, is_fence : UInt<1>, is_fencei : UInt<1>, is_store : UInt<1>, is_amo : UInt<1>, is_load : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_if : UInt<1>, replay_if : UInt<1>, debug_wdata : UInt<64>, debug_events : {fetch_seq : UInt<32>}}, flags : UInt<5>}}[2], flip lxcpt : {valid : UInt<1>, bits : {uop : {valid : UInt<1>, iw_state : UInt<2>, uopc : UInt<9>, inst : UInt<32>, pc : UInt<40>, fu_code : UInt<8>, ctrl : {br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<4>, fcn_dw : UInt<1>, rf_wen : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, wakeup_delay : UInt<2>, allocate_brtag : UInt<1>, is_br_or_jmp : UInt<1>, is_jump : UInt<1>, is_jal : UInt<1>, is_ret : UInt<1>, is_call : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, br_prediction : {bpd_predict_val : UInt<1>, bpd_predict_taken : UInt<1>, btb_hit : UInt<1>, btb_predicted : UInt<1>, is_br_or_jalr : UInt<1>}, stat_brjmp_mispredicted : UInt<1>, stat_btb_made_pred : UInt<1>, stat_btb_mispredicted : UInt<1>, stat_bpd_made_pred : UInt<1>, stat_bpd_mispredicted : UInt<1>, fetch_pc_lob : UInt<3>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, brob_idx : UInt<5>, pdst : UInt<7>, pop1 : UInt<7>, pop2 : UInt<7>, pop3 : UInt<7>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<4>, mem_typ : UInt<3>, is_fence : UInt<1>, is_fencei : UInt<1>, is_store : UInt<1>, is_amo : UInt<1>, is_load : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_if : UInt<1>, replay_if : UInt<1>, debug_wdata : UInt<64>, debug_events : {fetch_seq : UInt<32>}}, cause : UInt<4>, badvaddr : UInt<40>}}, flip bxcpt : {valid : UInt<1>, bits : {uop : {valid : UInt<1>, iw_state : UInt<2>, uopc : UInt<9>, inst : UInt<32>, pc : UInt<40>, fu_code : UInt<8>, ctrl : {br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<4>, fcn_dw : UInt<1>, rf_wen : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, wakeup_delay : UInt<2>, allocate_brtag : UInt<1>, is_br_or_jmp : UInt<1>, is_jump : UInt<1>, is_jal : UInt<1>, is_ret : UInt<1>, is_call : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, br_prediction : {bpd_predict_val : UInt<1>, bpd_predict_taken : UInt<1>, btb_hit : UInt<1>, btb_predicted : UInt<1>, is_br_or_jalr : UInt<1>}, stat_brjmp_mispredicted : UInt<1>, stat_btb_made_pred : UInt<1>, stat_btb_mispredicted : UInt<1>, stat_bpd_made_pred : UInt<1>, stat_bpd_mispredicted : UInt<1>, fetch_pc_lob : UInt<3>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, brob_idx : UInt<5>, pdst : UInt<7>, pop1 : UInt<7>, pop2 : UInt<7>, pop3 : UInt<7>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<4>, mem_typ : UInt<3>, is_fence : UInt<1>, is_fencei : UInt<1>, is_store : UInt<1>, is_amo : UInt<1>, is_load : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_if : UInt<1>, replay_if : UInt<1>, debug_wdata : UInt<64>, debug_events : {fetch_seq : UInt<32>}}, cause : UInt<4>, badvaddr : UInt<40>}}, flip cxcpt : {valid : UInt<1>, bits : {uop : {valid : UInt<1>, iw_state : UInt<2>, uopc : UInt<9>, inst : UInt<32>, pc : UInt<40>, fu_code : UInt<8>, ctrl : {br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<4>, fcn_dw : UInt<1>, rf_wen : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, wakeup_delay : UInt<2>, allocate_brtag : UInt<1>, is_br_or_jmp : UInt<1>, is_jump : UInt<1>, is_jal : UInt<1>, is_ret : UInt<1>, is_call : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, br_prediction : {bpd_predict_val : UInt<1>, bpd_predict_taken : UInt<1>, btb_hit : UInt<1>, btb_predicted : UInt<1>, is_br_or_jalr : UInt<1>}, stat_brjmp_mispredicted : UInt<1>, stat_btb_made_pred : UInt<1>, stat_btb_mispredicted : UInt<1>, stat_bpd_made_pred : UInt<1>, stat_bpd_mispredicted : UInt<1>, fetch_pc_lob : UInt<3>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, brob_idx : UInt<5>, pdst : UInt<7>, pop1 : UInt<7>, pop2 : UInt<7>, pop3 : UInt<7>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<4>, mem_typ : UInt<3>, is_fence : UInt<1>, is_fencei : UInt<1>, is_store : UInt<1>, is_amo : UInt<1>, is_load : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_if : UInt<1>, replay_if : UInt<1>, debug_wdata : UInt<64>, debug_events : {fetch_seq : UInt<32>}}, cause : UInt<4>, badvaddr : UInt<40>}}, com_valids : UInt<1>[2], com_uops : {valid : UInt<1>, iw_state : UInt<2>, uopc : UInt<9>, inst : UInt<32>, pc : UInt<40>, fu_code : UInt<8>, ctrl : {br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<4>, fcn_dw : UInt<1>, rf_wen : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, wakeup_delay : UInt<2>, allocate_brtag : UInt<1>, is_br_or_jmp : UInt<1>, is_jump : UInt<1>, is_jal : UInt<1>, is_ret : UInt<1>, is_call : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, br_prediction : {bpd_predict_val : UInt<1>, bpd_predict_taken : UInt<1>, btb_hit : UInt<1>, btb_predicted : UInt<1>, is_br_or_jalr : UInt<1>}, stat_brjmp_mispredicted : UInt<1>, stat_btb_made_pred : UInt<1>, stat_btb_mispredicted : UInt<1>, stat_bpd_made_pred : UInt<1>, stat_bpd_mispredicted : UInt<1>, fetch_pc_lob : UInt<3>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, brob_idx : UInt<5>, pdst : UInt<7>, pop1 : UInt<7>, pop2 : UInt<7>, pop3 : UInt<7>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<4>, mem_typ : UInt<3>, is_fence : UInt<1>, is_fencei : UInt<1>, is_store : UInt<1>, is_amo : UInt<1>, is_load : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_if : UInt<1>, replay_if : UInt<1>, debug_wdata : UInt<64>, debug_events : {fetch_seq : UInt<32>}}[2], com_fflags_val : UInt<1>, com_fflags : UInt<5>, com_st_mask : UInt<1>[2], com_ld_mask : UInt<1>[2], flip lsu_clr_bsy_valid : UInt<1>, flip lsu_clr_bsy_rob_idx : UInt<6>, com_load_is_at_rob_head : UInt<1>, com_exception : UInt<1>, com_exc_cause : UInt<64>, com_handling_exc : UInt<1>, com_rbk_valids : UInt<1>[2], com_badvaddr : UInt<64>, flip brinfo : {valid : UInt<1>, mispredict : UInt<1>, mask : UInt<8>, tag : UInt<3>, exe_mask : UInt<8>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, taken : UInt<1>, is_jr : UInt<1>, btb_made_pred : UInt<1>, btb_mispredict : UInt<1>, bpd_made_pred : UInt<1>, bpd_mispredict : UInt<1>}, get_pc : {flip rob_idx : UInt<6>, curr_pc : UInt<40>, curr_brob_idx : UInt<5>, next_val : UInt<1>, next_pc : UInt<40>}, lsu_misspec : UInt<1>, flush_take_pc : UInt<1>, flush_pc : UInt<40>, flush_pipeline : UInt<1>, flush_brob : UInt<1>, empty : UInt<1>, ready : UInt<1>, brob_deallocate : {valid : UInt<1>, bits : {brob_idx : UInt<5>}}, debug : {state : UInt, rob_head : UInt<6>, xcpt_val : UInt<1>, xcpt_uop : {valid : UInt<1>, iw_state : UInt<2>, uopc : UInt<9>, inst : UInt<32>, pc : UInt<40>, fu_code : UInt<8>, ctrl : {br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<4>, fcn_dw : UInt<1>, rf_wen : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, wakeup_delay : UInt<2>, allocate_brtag : UInt<1>, is_br_or_jmp : UInt<1>, is_jump : UInt<1>, is_jal : UInt<1>, is_ret : UInt<1>, is_call : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, br_prediction : {bpd_predict_val : UInt<1>, bpd_predict_taken : UInt<1>, btb_hit : UInt<1>, btb_predicted : UInt<1>, is_br_or_jalr : UInt<1>}, stat_brjmp_mispredicted : UInt<1>, stat_btb_made_pred : UInt<1>, stat_btb_mispredicted : UInt<1>, stat_bpd_made_pred : UInt<1>, stat_bpd_mispredicted : UInt<1>, fetch_pc_lob : UInt<3>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, brob_idx : UInt<5>, pdst : UInt<7>, pop1 : UInt<7>, pop2 : UInt<7>, pop3 : UInt<7>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<4>, mem_typ : UInt<3>, is_fence : UInt<1>, is_fencei : UInt<1>, is_store : UInt<1>, is_amo : UInt<1>, is_load : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_if : UInt<1>, replay_if : UInt<1>, debug_wdata : UInt<64>, debug_events : {fetch_seq : UInt<32>}}, xcpt_badvaddr : UInt<64>}, flip debug_tsc : UInt<64>}
io is invalid
reg rob_state : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
reg rob_head : UInt<5>, clk with : (reset => (reset, UInt<5>("h00")))
reg rob_tail : UInt<5>, clk with : (reset => (reset, UInt<5>("h00")))
node rob_tail_idx = dshl(rob_tail, UInt<1>("h01")) @[rob.scala 192:32]
wire will_commit : UInt<1>[2] @[rob.scala 194:34]
will_commit is invalid @[rob.scala 194:34]
wire can_commit : UInt<1>[2] @[rob.scala 195:34]
can_commit is invalid @[rob.scala 195:34]
wire can_throw_exception : UInt<1>[2] @[rob.scala 196:34]
can_throw_exception is invalid @[rob.scala 196:34]
wire rob_head_vals : UInt<1>[2] @[rob.scala 197:34]
rob_head_vals is invalid @[rob.scala 197:34]
wire rob_head_is_store : UInt<1>[2] @[rob.scala 198:34]
rob_head_is_store is invalid @[rob.scala 198:34]
wire rob_head_is_load : UInt<1>[2] @[rob.scala 199:34]
rob_head_is_load is invalid @[rob.scala 199:34]
wire rob_head_is_branch : UInt<1>[2] @[rob.scala 200:34]
rob_head_is_branch is invalid @[rob.scala 200:34]
wire rob_head_fflags : UInt<5>[2] @[rob.scala 201:34]
rob_head_fflags is invalid @[rob.scala 201:34]
wire rob_brt_vals : UInt<1>[2] @[rob.scala 206:34]
rob_brt_vals is invalid @[rob.scala 206:34]
wire refetch_inst : UInt<1> @[rob.scala 208:31]
refetch_inst is invalid @[rob.scala 208:31]
reg r_xcpt_val : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
reg r_xcpt_uop : {valid : UInt<1>, iw_state : UInt<2>, uopc : UInt<9>, inst : UInt<32>, pc : UInt<40>, fu_code : UInt<8>, ctrl : {br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<4>, fcn_dw : UInt<1>, rf_wen : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, wakeup_delay : UInt<2>, allocate_brtag : UInt<1>, is_br_or_jmp : UInt<1>, is_jump : UInt<1>, is_jal : UInt<1>, is_ret : UInt<1>, is_call : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, br_prediction : {bpd_predict_val : UInt<1>, bpd_predict_taken : UInt<1>, btb_hit : UInt<1>, btb_predicted : UInt<1>, is_br_or_jalr : UInt<1>}, stat_brjmp_mispredicted : UInt<1>, stat_btb_made_pred : UInt<1>, stat_btb_mispredicted : UInt<1>, stat_bpd_made_pred : UInt<1>, stat_bpd_mispredicted : UInt<1>, fetch_pc_lob : UInt<3>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, brob_idx : UInt<5>, pdst : UInt<7>, pop1 : UInt<7>, pop2 : UInt<7>, pop3 : UInt<7>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<4>, mem_typ : UInt<3>, is_fence : UInt<1>, is_fencei : UInt<1>, is_store : UInt<1>, is_amo : UInt<1>, is_load : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_if : UInt<1>, replay_if : UInt<1>, debug_wdata : UInt<64>, debug_events : {fetch_seq : UInt<32>}}, clk
reg r_xcpt_badvaddr : UInt<40>, clk
wire debug_entry : {valid : UInt<1>, busy : UInt<1>, uop : {valid : UInt<1>, iw_state : UInt<2>, uopc : UInt<9>, inst : UInt<32>, pc : UInt<40>, fu_code : UInt<8>, ctrl : {br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<4>, fcn_dw : UInt<1>, rf_wen : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, wakeup_delay : UInt<2>, allocate_brtag : UInt<1>, is_br_or_jmp : UInt<1>, is_jump : UInt<1>, is_jal : UInt<1>, is_ret : UInt<1>, is_call : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, br_prediction : {bpd_predict_val : UInt<1>, bpd_predict_taken : UInt<1>, btb_hit : UInt<1>, btb_predicted : UInt<1>, is_br_or_jalr : UInt<1>}, stat_brjmp_mispredicted : UInt<1>, stat_btb_made_pred : UInt<1>, stat_btb_mispredicted : UInt<1>, stat_bpd_made_pred : UInt<1>, stat_bpd_mispredicted : UInt<1>, fetch_pc_lob : UInt<3>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, brob_idx : UInt<5>, pdst : UInt<7>, pop1 : UInt<7>, pop2 : UInt<7>, pop3 : UInt<7>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<4>, mem_typ : UInt<3>, is_fence : UInt<1>, is_fencei : UInt<1>, is_store : UInt<1>, is_amo : UInt<1>, is_load : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_if : UInt<1>, replay_if : UInt<1>, debug_wdata : UInt<64>, debug_events : {fetch_seq : UInt<32>}}, exception : UInt<1>}[48] @[rob.scala 240:26]
debug_entry is invalid @[rob.scala 240:26]
cmem T_23555 : UInt<37>[12] @[rob.scala 893:22]
cmem T_23558 : UInt<37>[12] @[rob.scala 894:22]
node T_23559 = or(io.dis_valids[0], io.dis_valids[1]) @[rob.scala 260:32]
when T_23559 : @[rob.scala 261:4]
node T_23560 = bits(io.dis_uops[0].pc, 39, 0) @[rob.scala 931:28]
node T_23562 = dshr(T_23560, UInt<2>("h03")) @[rob.scala 931:42]
node T_23563 = bits(rob_tail, 0, 0) @[rob.scala 932:25]
when T_23563 : @[rob.scala 933:10]
node T_23565 = dshr(rob_tail, UInt<1>("h01")) @[rob.scala 934:29]
infer mport T_23566 = T_23558[T_23565], clk
T_23566 <= T_23562 @[rob.scala 934:41]
skip @[rob.scala 933:10]
node T_23568 = eq(T_23563, UInt<1>("h00")) @[rob.scala 933:10]
when T_23568 : @[rob.scala 937:10]
node T_23570 = dshr(rob_tail, UInt<1>("h01")) @[rob.scala 938:29]
infer mport T_23571 = T_23555[T_23570], clk
T_23571 <= T_23562 @[rob.scala 938:41]
skip @[rob.scala 937:10]
skip @[rob.scala 261:4]
node T_23573 = dshr(io.get_pc.rob_idx, UInt<1>("h01")) @[rob.scala 222:27]
node T_23574 = bits(T_23573, 0, 0) @[rob.scala 913:37]
node T_23576 = dshr(T_23573, UInt<1>("h01")) @[rob.scala 913:58]
node T_23578 = eq(T_23576, UInt<4>("h0b")) @[util.scala 75:28]
node T_23581 = add(T_23576, UInt<1>("h01")) @[util.scala 76:35]
node T_23582 = tail(T_23581, 1) @[util.scala 76:35]
node T_23583 = mux(T_23578, UInt<1>("h00"), T_23582) @[util.scala 76:13]
node T_23585 = dshr(T_23573, UInt<1>("h01")) @[rob.scala 914:50]
node T_23586 = mux(T_23574, T_23583, T_23585) @[rob.scala 913:29]
infer mport T_23587 = T_23555[T_23586], clk
node T_23589 = dshl(T_23587, UInt<2>("h03")) @[rob.scala 915:39]
node T_23591 = dshr(T_23573, UInt<1>("h01")) @[rob.scala 916:36]
infer mport T_23592 = T_23558[T_23591], clk
node T_23594 = dshl(T_23592, UInt<2>("h03")) @[rob.scala 916:48]
wire T_23596 : UInt<64> @[rob.scala 918:28]
T_23596 is invalid @[rob.scala 918:28]
wire T_23598 : UInt<64> @[rob.scala 919:28]
T_23598 is invalid @[rob.scala 919:28]
node T_23599 = bits(T_23573, 0, 0) @[rob.scala 920:32]
node T_23600 = mux(T_23599, T_23594, T_23589) @[rob.scala 920:24]
T_23596 <= T_23600 @[rob.scala 920:18]
node T_23601 = bits(T_23573, 0, 0) @[rob.scala 921:32]
node T_23602 = mux(T_23601, T_23589, T_23594) @[rob.scala 921:24]
T_23598 <= T_23602 @[rob.scala 921:18]
node T_23603 = bits(T_23596, 39, 0) @[rob.scala 922:40]
node T_23604 = bits(T_23603, 39, 39) @[util.scala 114:43]
node T_23605 = bits(T_23604, 0, 0) @[Bitwise.scala 33:15]
node T_23608 = mux(T_23605, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 33:12]
node curr_row_pc = cat(T_23608, T_23603) @[Cat.scala 20:58]
node T_23609 = bits(T_23598, 39, 0) @[rob.scala 923:40]
node T_23610 = bits(T_23609, 39, 39) @[util.scala 114:43]
node T_23611 = bits(T_23610, 0, 0) @[Bitwise.scala 33:15]
node T_23614 = mux(T_23611, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 33:12]
node next_row_pc = cat(T_23614, T_23609) @[Cat.scala 20:58]
node T_23615 = bits(io.get_pc.rob_idx, 0, 0) @[rob.scala 227:38]
node T_23617 = cat(T_23615, UInt<2>("h00")) @[Cat.scala 20:58]
node T_23618 = add(curr_row_pc, T_23617) @[rob.scala 268:37]
node T_23619 = tail(T_23618, 1) @[rob.scala 268:37]
io.get_pc.curr_pc <= T_23619 @[rob.scala 268:22]
node T_23620 = cat(rob_brt_vals[1], rob_brt_vals[0])
node T_23621 = bits(T_23620, 0, 0) @[OneHot.scala 35:40]
node T_23622 = bits(T_23620, 1, 1) @[OneHot.scala 35:40]
node next_bank_idx = mux(T_23621, UInt<1>("h00"), UInt<1>("h01")) @[Mux.scala 31:69]
node rob_pc_hob_next_val = or(rob_brt_vals[0], rob_brt_vals[1]) @[rob.scala 273:51]
node T_23625 = cat(io.dis_valids[1], io.dis_valids[0])
node T_23626 = bits(T_23625, 0, 0) @[OneHot.scala 35:40]
node T_23627 = bits(T_23625, 1, 1) @[OneHot.scala 35:40]
node bypass_next_bank_idx = mux(T_23626, UInt<1>("h00"), UInt<1>("h01")) @[Mux.scala 31:69]
node T_23630 = asSInt(io.dis_uops[0].pc)
node T_23632 = and(T_23630, asSInt(UInt<4>("h08"))) @[rob.scala 276:51]
node T_23633 = asSInt(T_23632) @[rob.scala 276:51]
node T_23634 = asUInt(T_23633)
node T_23636 = cat(bypass_next_bank_idx, UInt<2>("h00")) @[Cat.scala 20:58]
node T_23637 = add(T_23634, T_23636) @[rob.scala 276:97]
node bypass_next_pc = tail(T_23637, 1) @[rob.scala 276:97]
node T_23638 = or(io.dis_valids[0], io.dis_valids[1]) @[rob.scala 279:71]
node T_23639 = or(rob_pc_hob_next_val, T_23638) @[rob.scala 279:46]
io.get_pc.next_val <= T_23639 @[rob.scala 279:23]
node T_23641 = cat(next_bank_idx, UInt<2>("h00")) @[Cat.scala 20:58]
node T_23642 = add(next_row_pc, T_23641) @[rob.scala 281:40]
node T_23643 = tail(T_23642, 1) @[rob.scala 281:40]
node T_23644 = mux(rob_pc_hob_next_val, T_23643, bypass_next_pc) @[rob.scala 280:28]
io.get_pc.next_pc <= T_23644 @[rob.scala 280:22]
wire finished_committing_row : UInt<1> @[rob.scala 291:38]
finished_committing_row is invalid @[rob.scala 291:38]
reg r_partial_row : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
cmem row_metadata_brob_idx : UInt<5>[24] @[rob.scala 295:35]
cmem row_metadata_has_brorjalr : UInt<1>[24] @[rob.scala 296:38]
node T_23651 = or(io.dis_valids[0], io.dis_valids[1]) @[rob.scala 297:32]
node T_23652 = and(T_23651, io.dis_new_packet) @[rob.scala 297:36]
when T_23652 : @[rob.scala 298:4]
infer mport T_23653 = row_metadata_brob_idx[rob_tail], clk
T_23653 <= io.dis_uops[0].brob_idx @[rob.scala 299:39]
infer mport T_23654 = row_metadata_has_brorjalr[rob_tail], clk
T_23654 <= io.dis_has_br_or_jalr_in_packet @[rob.scala 300:43]
r_partial_row <= io.dis_partial_stall @[rob.scala 301:21]
skip @[rob.scala 298:4]
node T_23655 = or(io.dis_valids[0], io.dis_valids[1]) @[rob.scala 303:37]
node T_23657 = eq(io.dis_new_packet, UInt<1>("h00")) @[rob.scala 303:44]
node T_23658 = and(T_23655, T_23657) @[rob.scala 303:41]
node T_23660 = eq(T_23652, UInt<1>("h00")) @[rob.scala 298:4]
node T_23661 = and(T_23660, T_23658) @[rob.scala 304:4]
when T_23661 : @[rob.scala 304:4]
r_partial_row <= io.dis_partial_stall @[rob.scala 305:21]
skip @[rob.scala 304:4]
when io.flush_brob : @[rob.scala 309:4]
infer mport T_23662 = row_metadata_has_brorjalr[rob_tail], clk
T_23662 <= UInt<1>("h00") @[rob.scala 310:43]
skip @[rob.scala 309:4]
infer mport T_23664 = row_metadata_has_brorjalr[rob_head], clk
node T_23665 = and(finished_committing_row, T_23664) @[rob.scala 315:56]
io.brob_deallocate.valid <= T_23665 @[rob.scala 315:29]
infer mport T_23666 = row_metadata_brob_idx[rob_head], clk
io.brob_deallocate.bits.brob_idx <= T_23666 @[rob.scala 316:37]
node T_23668 = dshr(io.get_pc.rob_idx, UInt<1>("h01")) @[rob.scala 222:27]
infer mport T_23669 = row_metadata_brob_idx[T_23668], clk
io.get_pc.curr_brob_idx <= T_23669 @[rob.scala 318:28]
node T_23670 = and(io.dis_valids[0], io.dis_uops[0].is_unique) @[rob.scala 322:24]
node T_23671 = and(io.dis_valids[1], io.dis_uops[1].is_unique) @[rob.scala 322:24]
node T_23672 = or(T_23670, T_23671) @[rob.scala 322:61]
io.flush_brob <= T_23672 @[rob.scala 321:18]
wire T_23702 : UInt<1>[24] @[rob.scala 334:60]
T_23702 is invalid @[rob.scala 334:60]
T_23702[0] <= UInt<1>("h00") @[rob.scala 334:60]
T_23702[1] <= UInt<1>("h00") @[rob.scala 334:60]
T_23702[2] <= UInt<1>("h00") @[rob.scala 334:60]
T_23702[3] <= UInt<1>("h00") @[rob.scala 334:60]
T_23702[4] <= UInt<1>("h00") @[rob.scala 334:60]
T_23702[5] <= UInt<1>("h00") @[rob.scala 334:60]
T_23702[6] <= UInt<1>("h00") @[rob.scala 334:60]
T_23702[7] <= UInt<1>("h00") @[rob.scala 334:60]
T_23702[8] <= UInt<1>("h00") @[rob.scala 334:60]
T_23702[9] <= UInt<1>("h00") @[rob.scala 334:60]
T_23702[10] <= UInt<1>("h00") @[rob.scala 334:60]
T_23702[11] <= UInt<1>("h00") @[rob.scala 334:60]
T_23702[12] <= UInt<1>("h00") @[rob.scala 334:60]
T_23702[13] <= UInt<1>("h00") @[rob.scala 334:60]
T_23702[14] <= UInt<1>("h00") @[rob.scala 334:60]
T_23702[15] <= UInt<1>("h00") @[rob.scala 334:60]
T_23702[16] <= UInt<1>("h00") @[rob.scala 334:60]
T_23702[17] <= UInt<1>("h00") @[rob.scala 334:60]
T_23702[18] <= UInt<1>("h00") @[rob.scala 334:60]
T_23702[19] <= UInt<1>("h00") @[rob.scala 334:60]
T_23702[20] <= UInt<1>("h00") @[rob.scala 334:60]
T_23702[21] <= UInt<1>("h00") @[rob.scala 334:60]
T_23702[22] <= UInt<1>("h00") @[rob.scala 334:60]
T_23702[23] <= UInt<1>("h00") @[rob.scala 334:60]
reg T_23706 : UInt<1>[24], clk with : (reset => (reset, T_23702))
cmem T_23710 : UInt<1>[24] @[rob.scala 335:30]
reg T_26182 : {valid : UInt<1>, iw_state : UInt<2>, uopc : UInt<9>, inst : UInt<32>, pc : UInt<40>, fu_code : UInt<8>, ctrl : {br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<4>, fcn_dw : UInt<1>, rf_wen : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, wakeup_delay : UInt<2>, allocate_brtag : UInt<1>, is_br_or_jmp : UInt<1>, is_jump : UInt<1>, is_jal : UInt<1>, is_ret : UInt<1>, is_call : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, br_prediction : {bpd_predict_val : UInt<1>, bpd_predict_taken : UInt<1>, btb_hit : UInt<1>, btb_predicted : UInt<1>, is_br_or_jalr : UInt<1>}, stat_brjmp_mispredicted : UInt<1>, stat_btb_made_pred : UInt<1>, stat_btb_mispredicted : UInt<1>, stat_bpd_made_pred : UInt<1>, stat_bpd_mispredicted : UInt<1>, fetch_pc_lob : UInt<3>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, brob_idx : UInt<5>, pdst : UInt<7>, pop1 : UInt<7>, pop2 : UInt<7>, pop3 : UInt<7>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<4>, mem_typ : UInt<3>, is_fence : UInt<1>, is_fencei : UInt<1>, is_store : UInt<1>, is_amo : UInt<1>, is_load : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_if : UInt<1>, replay_if : UInt<1>, debug_wdata : UInt<64>, debug_events : {fetch_seq : UInt<32>}}[24], clk
cmem T_28311 : UInt<1>[24] @[rob.scala 339:30]
cmem T_28314 : UInt<5>[24] @[rob.scala 340:30]
when io.dis_valids[0] : @[rob.scala 346:7]
T_23706[rob_tail] <= UInt<1>("h01") @[rob.scala 347:34]
infer mport T_28316 = T_23710[rob_tail], clk
node T_28318 = eq(io.dis_uops[0].is_fence, UInt<1>("h00")) @[rob.scala 348:37]
node T_28320 = eq(io.dis_uops[0].is_fencei, UInt<1>("h00")) @[rob.scala 349:37]
node T_28321 = and(T_28318, T_28320) @[rob.scala 348:62]
T_28316 <= T_28321 @[rob.scala 348:34]
T_26182[rob_tail] <- io.dis_uops[0] @[rob.scala 350:34]
infer mport T_28407 = T_28311[rob_tail], clk
T_28407 <= io.dis_uops[0].exception @[rob.scala 351:34]
infer mport T_28408 = T_28314[rob_tail], clk
T_28408 <= UInt<1>("h00") @[rob.scala 352:34]
T_26182[rob_tail].stat_brjmp_mispredicted <= UInt<1>("h00") @[rob.scala 353:52]
skip @[rob.scala 346:7]
node T_28496 = or(io.dis_valids[0], io.dis_valids[1]) @[rob.scala 355:40]
node T_28498 = eq(T_23706[rob_tail], UInt<1>("h00")) @[rob.scala 355:47]
node T_28499 = and(T_28496, T_28498) @[rob.scala 355:44]
node T_28501 = eq(io.dis_valids[0], UInt<1>("h00")) @[rob.scala 346:7]
node T_28502 = and(T_28501, T_28499) @[rob.scala 356:7]
when T_28502 : @[rob.scala 356:7]
T_26182[rob_tail].inst <= UInt<32>("h04033") @[rob.scala 357:33]
skip @[rob.scala 356:7]
node T_28589 = dshr(io.wb_resps[0].bits.uop.rob_idx, UInt<1>("h01")) @[rob.scala 222:27]
node T_28590 = bits(io.wb_resps[0].bits.uop.rob_idx, 0, 0) @[rob.scala 227:38]
node T_28592 = eq(T_28590, UInt<1>("h00")) @[rob.scala 331:55]
node T_28593 = and(io.wb_resps[0].valid, T_28592) @[rob.scala 368:30]
when T_28593 : @[rob.scala 369:10]
infer mport T_28594 = T_23710[T_28589], clk
T_28594 <= UInt<1>("h00") @[rob.scala 370:30]
skip @[rob.scala 369:10]
node T_28597 = dshr(io.wb_resps[1].bits.uop.rob_idx, UInt<1>("h01")) @[rob.scala 222:27]
node T_28598 = bits(io.wb_resps[1].bits.uop.rob_idx, 0, 0) @[rob.scala 227:38]
node T_28600 = eq(T_28598, UInt<1>("h00")) @[rob.scala 331:55]
node T_28601 = and(io.wb_resps[1].valid, T_28600) @[rob.scala 368:30]
when T_28601 : @[rob.scala 369:10]
infer mport T_28602 = T_23710[T_28597], clk
T_28602 <= UInt<1>("h00") @[rob.scala 370:30]
skip @[rob.scala 369:10]
node T_28605 = dshr(io.wb_resps[2].bits.uop.rob_idx, UInt<1>("h01")) @[rob.scala 222:27]
node T_28606 = bits(io.wb_resps[2].bits.uop.rob_idx, 0, 0) @[rob.scala 227:38]
node T_28608 = eq(T_28606, UInt<1>("h00")) @[rob.scala 331:55]
node T_28609 = and(io.wb_resps[2].valid, T_28608) @[rob.scala 368:30]
when T_28609 : @[rob.scala 369:10]
infer mport T_28610 = T_23710[T_28605], clk
T_28610 <= UInt<1>("h00") @[rob.scala 370:30]
skip @[rob.scala 369:10]
node T_28612 = bits(io.lsu_clr_bsy_rob_idx, 0, 0) @[rob.scala 227:38]
node T_28614 = eq(T_28612, UInt<1>("h00")) @[rob.scala 331:55]
node T_28615 = and(io.lsu_clr_bsy_valid, T_28614) @[rob.scala 388:34]
when T_28615 : @[rob.scala 389:7]
node T_28617 = dshr(io.lsu_clr_bsy_rob_idx, UInt<1>("h01")) @[rob.scala 222:27]
infer mport T_28618 = T_23710[T_28617], clk
T_28618 <= UInt<1>("h00") @[rob.scala 390:53]
skip @[rob.scala 389:7]
node T_28620 = bits(io.brinfo.rob_idx, 0, 0) @[rob.scala 227:38]
node T_28622 = eq(T_28620, UInt<1>("h00")) @[rob.scala 331:55]
node T_28623 = and(io.brinfo.valid, T_28622) @[rob.scala 400:29]
when T_28623 : @[rob.scala 401:7]
node T_28625 = dshr(io.brinfo.rob_idx, UInt<1>("h01")) @[rob.scala 222:27]
T_26182[T_28625].stat_brjmp_mispredicted <= io.brinfo.mispredict @[rob.scala 402:72]
node T_28712 = dshr(io.brinfo.rob_idx, UInt<1>("h01")) @[rob.scala 222:27]
T_26182[T_28712].stat_btb_mispredicted <= io.brinfo.btb_mispredict @[rob.scala 403:72]
node T_28799 = dshr(io.brinfo.rob_idx, UInt<1>("h01")) @[rob.scala 222:27]
T_26182[T_28799].stat_btb_made_pred <= io.brinfo.btb_made_pred @[rob.scala 404:72]
node T_28886 = dshr(io.brinfo.rob_idx, UInt<1>("h01")) @[rob.scala 222:27]
T_26182[T_28886].stat_bpd_mispredicted <= io.brinfo.bpd_mispredict @[rob.scala 405:72]
node T_28973 = dshr(io.brinfo.rob_idx, UInt<1>("h01")) @[rob.scala 222:27]
T_26182[T_28973].stat_bpd_made_pred <= io.brinfo.bpd_made_pred @[rob.scala 406:72]
skip @[rob.scala 401:7]
node T_29059 = bits(io.fflags[0].bits.uop.rob_idx, 0, 0) @[rob.scala 227:38]
node T_29061 = eq(T_29059, UInt<1>("h00")) @[rob.scala 331:55]
node T_29062 = and(io.fflags[0].valid, T_29061) @[rob.scala 415:35]
when T_29062 : @[rob.scala 416:10]
node T_29064 = dshr(io.fflags[0].bits.uop.rob_idx, UInt<1>("h01")) @[rob.scala 222:27]
infer mport T_29065 = T_28314[T_29064], clk
T_29065 <= io.fflags[0].bits.flags @[rob.scala 417:54]
skip @[rob.scala 416:10]
node T_29066 = bits(io.fflags[1].bits.uop.rob_idx, 0, 0) @[rob.scala 227:38]
node T_29068 = eq(T_29066, UInt<1>("h00")) @[rob.scala 331:55]
node T_29069 = and(io.fflags[1].valid, T_29068) @[rob.scala 415:35]
when T_29069 : @[rob.scala 416:10]
node T_29071 = dshr(io.fflags[1].bits.uop.rob_idx, UInt<1>("h01")) @[rob.scala 222:27]
infer mport T_29072 = T_28314[T_29071], clk
T_29072 <= io.fflags[1].bits.flags @[rob.scala 417:54]
skip @[rob.scala 416:10]
node T_29073 = bits(io.lxcpt.bits.uop.rob_idx, 0, 0) @[rob.scala 227:38]
node T_29075 = eq(T_29073, UInt<1>("h00")) @[rob.scala 331:55]
node T_29076 = and(io.lxcpt.valid, T_29075) @[rob.scala 425:28]
when T_29076 : @[rob.scala 426:7]
node T_29078 = dshr(io.lxcpt.bits.uop.rob_idx, UInt<1>("h01")) @[rob.scala 222:27]
infer mport T_29079 = T_28311[T_29078], clk
T_29079 <= UInt<1>("h01") @[rob.scala 427:62]
skip @[rob.scala 426:7]
node T_29081 = bits(io.bxcpt.bits.uop.rob_idx, 0, 0) @[rob.scala 227:38]
node T_29083 = eq(T_29081, UInt<1>("h00")) @[rob.scala 331:55]
node T_29084 = and(io.bxcpt.valid, T_29083) @[rob.scala 429:28]
when T_29084 : @[rob.scala 430:7]
node T_29086 = dshr(io.bxcpt.bits.uop.rob_idx, UInt<1>("h01")) @[rob.scala 222:27]
infer mport T_29087 = T_28311[T_29086], clk
T_29087 <= UInt<1>("h01") @[rob.scala 431:62]
skip @[rob.scala 430:7]
infer mport T_29089 = T_28311[rob_head], clk
node T_29090 = and(T_23706[rob_head], T_29089) @[rob.scala 433:51]
can_throw_exception[0] <= T_29090 @[rob.scala 433:30]
infer mport T_29091 = T_23710[rob_head], clk
node T_29093 = eq(T_29091, UInt<1>("h00")) @[rob.scala 439:45]
node T_29094 = and(T_23706[rob_head], T_29093) @[rob.scala 439:42]
can_commit[0] <= T_29094 @[rob.scala 439:21]
wire T_29096 : UInt @[rob.scala 441:25]
T_29096 is invalid @[rob.scala 441:25]
T_29096 <= rob_head @[rob.scala 442:15]
node T_29097 = eq(rob_state, UInt<2>("h02")) @[rob.scala 443:23]
when T_29097 : @[rob.scala 444:7]
T_29096 <= rob_tail @[rob.scala 445:18]
skip @[rob.scala 444:7]
io.com_valids[0] <= will_commit[0] @[rob.scala 450:28]
node T_29098 = eq(rob_state, UInt<2>("h02")) @[rob.scala 451:42]
node T_29099 = and(T_29098, T_23706[T_29096]) @[rob.scala 451:58]
node T_29185 = eq(T_26182[T_29096].dst_rtype, UInt<2>("h00")) @[rob.scala 453:59]
node T_29271 = eq(T_26182[T_29096].dst_rtype, UInt<2>("h01")) @[rob.scala 453:100]
node T_29272 = or(T_29185, T_29271) @[rob.scala 453:70]
node T_29273 = and(T_29099, T_29272) @[rob.scala 452:48]
node T_29275 = and(T_29273, UInt<1>("h01")) @[rob.scala 453:112]
io.com_rbk_valids[0] <= T_29275 @[rob.scala 451:28]
io.com_uops[0] <- T_26182[T_29096] @[rob.scala 455:28]
node T_29361 = eq(rob_state, UInt<2>("h02")) @[rob.scala 457:23]
when T_29361 : @[rob.scala 458:7]
T_23706[T_29096] <= UInt<1>("h00") @[rob.scala 459:33]
infer mport T_29363 = T_28311[T_29096], clk
T_29363 <= UInt<1>("h00") @[rob.scala 460:33]
skip @[rob.scala 458:7]
node T_29365 = and(io.brinfo.mask, T_26182[0].br_mask) @[util.scala 45:52]
node T_29367 = neq(T_29365, UInt<1>("h00")) @[util.scala 45:60]
node T_29368 = and(T_23706[0], T_29367) @[rob.scala 481:39]
node T_29369 = and(io.brinfo.valid, io.brinfo.mispredict) @[rob.scala 484:32]
node T_29370 = and(T_29369, T_29368) @[rob.scala 484:56]
when T_29370 : @[rob.scala 485:10]
T_23706[0] <= UInt<1>("h00") @[rob.scala 486:24]
T_26182[UInt<1>("h00")].inst <= UInt<32>("h04033") @[rob.scala 487:35]
skip @[rob.scala 485:10]
node T_29459 = eq(io.brinfo.mispredict, UInt<1>("h00")) @[rob.scala 489:40]
node T_29460 = and(io.brinfo.valid, T_29459) @[rob.scala 489:37]
node T_29461 = and(T_29460, T_29368) @[rob.scala 489:62]
node T_29463 = eq(T_29370, UInt<1>("h00")) @[rob.scala 485:10]
node T_29464 = and(T_29463, T_29461) @[rob.scala 490:10]
when T_29464 : @[rob.scala 490:10]
node T_29465 = not(io.brinfo.mask) @[rob.scala 492:46]
node T_29466 = and(T_26182[0].br_mask, T_29465) @[rob.scala 492:44]
T_26182[0].br_mask <= T_29466 @[rob.scala 492:32]
skip @[rob.scala 490:10]
node T_29467 = and(io.brinfo.mask, T_26182[1].br_mask) @[util.scala 45:52]
node T_29469 = neq(T_29467, UInt<1>("h00")) @[util.scala 45:60]
node T_29470 = and(T_23706[1], T_29469) @[rob.scala 481:39]
node T_29471 = and(io.brinfo.valid, io.brinfo.mispredict) @[rob.scala 484:32]
node T_29472 = and(T_29471, T_29470) @[rob.scala 484:56]
when T_29472 : @[rob.scala 485:10]
T_23706[1] <= UInt<1>("h00") @[rob.scala 486:24]
T_26182[UInt<1>("h01")].inst <= UInt<32>("h04033") @[rob.scala 487:35]
skip @[rob.scala 485:10]
node T_29561 = eq(io.brinfo.mispredict, UInt<1>("h00")) @[rob.scala 489:40]
node T_29562 = and(io.brinfo.valid, T_29561) @[rob.scala 489:37]
node T_29563 = and(T_29562, T_29470) @[rob.scala 489:62]
node T_29565 = eq(T_29472, UInt<1>("h00")) @[rob.scala 485:10]
node T_29566 = and(T_29565, T_29563) @[rob.scala 490:10]
when T_29566 : @[rob.scala 490:10]
node T_29567 = not(io.brinfo.mask) @[rob.scala 492:46]
node T_29568 = and(T_26182[1].br_mask, T_29567) @[rob.scala 492:44]
T_26182[1].br_mask <= T_29568 @[rob.scala 492:32]
skip @[rob.scala 490:10]
node T_29569 = and(io.brinfo.mask, T_26182[2].br_mask) @[util.scala 45:52]
node T_29571 = neq(T_29569, UInt<1>("h00")) @[util.scala 45:60]
node T_29572 = and(T_23706[2], T_29571) @[rob.scala 481:39]
node T_29573 = and(io.brinfo.valid, io.brinfo.mispredict) @[rob.scala 484:32]
node T_29574 = and(T_29573, T_29572) @[rob.scala 484:56]
when T_29574 : @[rob.scala 485:10]
T_23706[2] <= UInt<1>("h00") @[rob.scala 486:24]
T_26182[UInt<2>("h02")].inst <= UInt<32>("h04033") @[rob.scala 487:35]
skip @[rob.scala 485:10]
node T_29663 = eq(io.brinfo.mispredict, UInt<1>("h00")) @[rob.scala 489:40]
node T_29664 = and(io.brinfo.valid, T_29663) @[rob.scala 489:37]
node T_29665 = and(T_29664, T_29572) @[rob.scala 489:62]
node T_29667 = eq(T_29574, UInt<1>("h00")) @[rob.scala 485:10]
node T_29668 = and(T_29667, T_29665) @[rob.scala 490:10]
when T_29668 : @[rob.scala 490:10]
node T_29669 = not(io.brinfo.mask) @[rob.scala 492:46]
node T_29670 = and(T_26182[2].br_mask, T_29669) @[rob.scala 492:44]
T_26182[2].br_mask <= T_29670 @[rob.scala 492:32]
skip @[rob.scala 490:10]
node T_29671 = and(io.brinfo.mask, T_26182[3].br_mask) @[util.scala 45:52]
node T_29673 = neq(T_29671, UInt<1>("h00")) @[util.scala 45:60]
node T_29674 = and(T_23706[3], T_29673) @[rob.scala 481:39]
node T_29675 = and(io.brinfo.valid, io.brinfo.mispredict) @[rob.scala 484:32]
node T_29676 = and(T_29675, T_29674) @[rob.scala 484:56]
when T_29676 : @[rob.scala 485:10]
T_23706[3] <= UInt<1>("h00") @[rob.scala 486:24]
T_26182[UInt<2>("h03")].inst <= UInt<32>("h04033") @[rob.scala 487:35]
skip @[rob.scala 485:10]
node T_29765 = eq(io.brinfo.mispredict, UInt<1>("h00")) @[rob.scala 489:40]
node T_29766 = and(io.brinfo.valid, T_29765) @[rob.scala 489:37]
node T_29767 = and(T_29766, T_29674) @[rob.scala 489:62]
node T_29769 = eq(T_29676, UInt<1>("h00")) @[rob.scala 485:10]
node T_29770 = and(T_29769, T_29767) @[rob.scala 490:10]
when T_29770 : @[rob.scala 490:10]
node T_29771 = not(io.brinfo.mask) @[rob.scala 492:46]
node T_29772 = and(T_26182[3].br_mask, T_29771) @[rob.scala 492:44]
T_26182[3].br_mask <= T_29772 @[rob.scala 492:32]
skip @[rob.scala 490:10]
node T_29773 = and(io.brinfo.mask, T_26182[4].br_mask) @[util.scala 45:52]
node T_29775 = neq(T_29773, UInt<1>("h00")) @[util.scala 45:60]
node T_29776 = and(T_23706[4], T_29775) @[rob.scala 481:39]
node T_29777 = and(io.brinfo.valid, io.brinfo.mispredict) @[rob.scala 484:32]
node T_29778 = and(T_29777, T_29776) @[rob.scala 484:56]
when T_29778 : @[rob.scala 485:10]
T_23706[4] <= UInt<1>("h00") @[rob.scala 486:24]
T_26182[UInt<3>("h04")].inst <= UInt<32>("h04033") @[rob.scala 487:35]
skip @[rob.scala 485:10]
node T_29867 = eq(io.brinfo.mispredict, UInt<1>("h00")) @[rob.scala 489:40]
node T_29868 = and(io.brinfo.valid, T_29867) @[rob.scala 489:37]
node T_29869 = and(T_29868, T_29776) @[rob.scala 489:62]
node T_29871 = eq(T_29778, UInt<1>("h00")) @[rob.scala 485:10]
node T_29872 = and(T_29871, T_29869) @[rob.scala 490:10]
when T_29872 : @[rob.scala 490:10]
node T_29873 = not(io.brinfo.mask) @[rob.scala 492:46]
node T_29874 = and(T_26182[4].br_mask, T_29873) @[rob.scala 492:44]
T_26182[4].br_mask <= T_29874 @[rob.scala 492:32]
skip @[rob.scala 490:10]
node T_29875 = and(io.brinfo.mask, T_26182[5].br_mask) @[util.scala 45:52]
node T_29877 = neq(T_29875, UInt<1>("h00")) @[util.scala 45:60]
node T_29878 = and(T_23706[5], T_29877) @[rob.scala 481:39]
node T_29879 = and(io.brinfo.valid, io.brinfo.mispredict) @[rob.scala 484:32]
node T_29880 = and(T_29879, T_29878) @[rob.scala 484:56]
when T_29880 : @[rob.scala 485:10]
T_23706[5] <= UInt<1>("h00") @[rob.scala 486:24]
T_26182[UInt<3>("h05")].inst <= UInt<32>("h04033") @[rob.scala 487:35]
skip @[rob.scala 485:10]
node T_29969 = eq(io.brinfo.mispredict, UInt<1>("h00")) @[rob.scala 489:40]
node T_29970 = and(io.brinfo.valid, T_29969) @[rob.scala 489:37]
node T_29971 = and(T_29970, T_29878) @[rob.scala 489:62]
node T_29973 = eq(T_29880, UInt<1>("h00")) @[rob.scala 485:10]
node T_29974 = and(T_29973, T_29971) @[rob.scala 490:10]
when T_29974 : @[rob.scala 490:10]
node T_29975 = not(io.brinfo.mask) @[rob.scala 492:46]
node T_29976 = and(T_26182[5].br_mask, T_29975) @[rob.scala 492:44]
T_26182[5].br_mask <= T_29976 @[rob.scala 492:32]
skip @[rob.scala 490:10]
node T_29977 = and(io.brinfo.mask, T_26182[6].br_mask) @[util.scala 45:52]
node T_29979 = neq(T_29977, UInt<1>("h00")) @[util.scala 45:60]
node T_29980 = and(T_23706[6], T_29979) @[rob.scala 481:39]
node T_29981 = and(io.brinfo.valid, io.brinfo.mispredict) @[rob.scala 484:32]
node T_29982 = and(T_29981, T_29980) @[rob.scala 484:56]
when T_29982 : @[rob.scala 485:10]
T_23706[6] <= UInt<1>("h00") @[rob.scala 486:24]
T_26182[UInt<3>("h06")].inst <= UInt<32>("h04033") @[rob.scala 487:35]
skip @[rob.scala 485:10]
node T_30071 = eq(io.brinfo.mispredict, UInt<1>("h00")) @[rob.scala 489:40]
node T_30072 = and(io.brinfo.valid, T_30071) @[rob.scala 489:37]
node T_30073 = and(T_30072, T_29980) @[rob.scala 489:62]
node T_30075 = eq(T_29982, UInt<1>("h00")) @[rob.scala 485:10]
node T_30076 = and(T_30075, T_30073) @[rob.scala 490:10]
when T_30076 : @[rob.scala 490:10]
node T_30077 = not(io.brinfo.mask) @[rob.scala 492:46]
node T_30078 = and(T_26182[6].br_mask, T_30077) @[rob.scala 492:44]
T_26182[6].br_mask <= T_30078 @[rob.scala 492:32]
skip @[rob.scala 490:10]
node T_30079 = and(io.brinfo.mask, T_26182[7].br_mask) @[util.scala 45:52]
node T_30081 = neq(T_30079, UInt<1>("h00")) @[util.scala 45:60]
node T_30082 = and(T_23706[7], T_30081) @[rob.scala 481:39]
node T_30083 = and(io.brinfo.valid, io.brinfo.mispredict) @[rob.scala 484:32]
node T_30084 = and(T_30083, T_30082) @[rob.scala 484:56]
when T_30084 : @[rob.scala 485:10]
T_23706[7] <= UInt<1>("h00") @[rob.scala 486:24]
T_26182[UInt<3>("h07")].inst <= UInt<32>("h04033") @[rob.scala 487:35]
skip @[rob.scala 485:10]
node T_30173 = eq(io.brinfo.mispredict, UInt<1>("h00")) @[rob.scala 489:40]
node T_30174 = and(io.brinfo.valid, T_30173) @[rob.scala 489:37]
node T_30175 = and(T_30174, T_30082) @[rob.scala 489:62]
node T_30177 = eq(T_30084, UInt<1>("h00")) @[rob.scala 485:10]
node T_30178 = and(T_30177, T_30175) @[rob.scala 490:10]
when T_30178 : @[rob.scala 490:10]
node T_30179 = not(io.brinfo.mask) @[rob.scala 492:46]
node T_30180 = and(T_26182[7].br_mask, T_30179) @[rob.scala 492:44]
T_26182[7].br_mask <= T_30180 @[rob.scala 492:32]
skip @[rob.scala 490:10]
node T_30181 = and(io.brinfo.mask, T_26182[8].br_mask) @[util.scala 45:52]
node T_30183 = neq(T_30181, UInt<1>("h00")) @[util.scala 45:60]
node T_30184 = and(T_23706[8], T_30183) @[rob.scala 481:39]
node T_30185 = and(io.brinfo.valid, io.brinfo.mispredict) @[rob.scala 484:32]
node T_30186 = and(T_30185, T_30184) @[rob.scala 484:56]
when T_30186 : @[rob.scala 485:10]
T_23706[8] <= UInt<1>("h00") @[rob.scala 486:24]
T_26182[UInt<4>("h08")].inst <= UInt<32>("h04033") @[rob.scala 487:35]
skip @[rob.scala 485:10]
node T_30275 = eq(io.brinfo.mispredict, UInt<1>("h00")) @[rob.scala 489:40]
node T_30276 = and(io.brinfo.valid, T_30275) @[rob.scala 489:37]
node T_30277 = and(T_30276, T_30184) @[rob.scala 489:62]
node T_30279 = eq(T_30186, UInt<1>("h00")) @[rob.scala 485:10]
node T_30280 = and(T_30279, T_30277) @[rob.scala 490:10]
when T_30280 : @[rob.scala 490:10]
node T_30281 = not(io.brinfo.mask) @[rob.scala 492:46]
node T_30282 = and(T_26182[8].br_mask, T_30281) @[rob.scala 492:44]
T_26182[8].br_mask <= T_30282 @[rob.scala 492:32]
skip @[rob.scala 490:10]
node T_30283 = and(io.brinfo.mask, T_26182[9].br_mask) @[util.scala 45:52]
node T_30285 = neq(T_30283, UInt<1>("h00")) @[util.scala 45:60]
node T_30286 = and(T_23706[9], T_30285) @[rob.scala 481:39]
node T_30287 = and(io.brinfo.valid, io.brinfo.mispredict) @[rob.scala 484:32]
node T_30288 = and(T_30287, T_30286) @[rob.scala 484:56]
when T_30288 : @[rob.scala 485:10]
T_23706[9] <= UInt<1>("h00") @[rob.scala 486:24]
T_26182[UInt<4>("h09")].inst <= UInt<32>("h04033") @[rob.scala 487:35]
skip @[rob.scala 485:10]
node T_30377 = eq(io.brinfo.mispredict, UInt<1>("h00")) @[rob.scala 489:40]
node T_30378 = and(io.brinfo.valid, T_30377) @[rob.scala 489:37]
node T_30379 = and(T_30378, T_30286) @[rob.scala 489:62]
node T_30381 = eq(T_30288, UInt<1>("h00")) @[rob.scala 485:10]
node T_30382 = and(T_30381, T_30379) @[rob.scala 490:10]
when T_30382 : @[rob.scala 490:10]
node T_30383 = not(io.brinfo.mask) @[rob.scala 492:46]
node T_30384 = and(T_26182[9].br_mask, T_30383) @[rob.scala 492:44]
T_26182[9].br_mask <= T_30384 @[rob.scala 492:32]
skip @[rob.scala 490:10]
node T_30385 = and(io.brinfo.mask, T_26182[10].br_mask) @[util.scala 45:52]
node T_30387 = neq(T_30385, UInt<1>("h00")) @[util.scala 45:60]
node T_30388 = and(T_23706[10], T_30387) @[rob.scala 481:39]
node T_30389 = and(io.brinfo.valid, io.brinfo.mispredict) @[rob.scala 484:32]
node T_30390 = and(T_30389, T_30388) @[rob.scala 484:56]
when T_30390 : @[rob.scala 485:10]
T_23706[10] <= UInt<1>("h00") @[rob.scala 486:24]
T_26182[UInt<4>("h0a")].inst <= UInt<32>("h04033") @[rob.scala 487:35]
skip @[rob.scala 485:10]
node T_30479 = eq(io.brinfo.mispredict, UInt<1>("h00")) @[rob.scala 489:40]
node T_30480 = and(io.brinfo.valid, T_30479) @[rob.scala 489:37]
node T_30481 = and(T_30480, T_30388) @[rob.scala 489:62]
node T_30483 = eq(T_30390, UInt<1>("h00")) @[rob.scala 485:10]
node T_30484 = and(T_30483, T_30481) @[rob.scala 490:10]
when T_30484 : @[rob.scala 490:10]
node T_30485 = not(io.brinfo.mask) @[rob.scala 492:46]
node T_30486 = and(T_26182[10].br_mask, T_30485) @[rob.scala 492:44]
T_26182[10].br_mask <= T_30486 @[rob.scala 492:32]
skip @[rob.scala 490:10]
node T_30487 = and(io.brinfo.mask, T_26182[11].br_mask) @[util.scala 45:52]
node T_30489 = neq(T_30487, UInt<1>("h00")) @[util.scala 45:60]
node T_30490 = and(T_23706[11], T_30489) @[rob.scala 481:39]
node T_30491 = and(io.brinfo.valid, io.brinfo.mispredict) @[rob.scala 484:32]
node T_30492 = and(T_30491, T_30490) @[rob.scala 484:56]
when T_30492 : @[rob.scala 485:10]
T_23706[11] <= UInt<1>("h00") @[rob.scala 486:24]
T_26182[UInt<4>("h0b")].inst <= UInt<32>("h04033") @[rob.scala 487:35]
skip @[rob.scala 485:10]
node T_30581 = eq(io.brinfo.mispredict, UInt<1>("h00")) @[rob.scala 489:40]
node T_30582 = and(io.brinfo.valid, T_30581) @[rob.scala 489:37]
node T_30583 = and(T_30582, T_30490) @[rob.scala 489:62]
node T_30585 = eq(T_30492, UInt<1>("h00")) @[rob.scala 485:10]
node T_30586 = and(T_30585, T_30583) @[rob.scala 490:10]
when T_30586 : @[rob.scala 490:10]
node T_30587 = not(io.brinfo.mask) @[rob.scala 492:46]
node T_30588 = and(T_26182[11].br_mask, T_30587) @[rob.scala 492:44]
T_26182[11].br_mask <= T_30588 @[rob.scala 492:32]
skip @[rob.scala 490:10]
node T_30589 = and(io.brinfo.mask, T_26182[12].br_mask) @[util.scala 45:52]
node T_30591 = neq(T_30589, UInt<1>("h00")) @[util.scala 45:60]
node T_30592 = and(T_23706[12], T_30591) @[rob.scala 481:39]
node T_30593 = and(io.brinfo.valid, io.brinfo.mispredict) @[rob.scala 484:32]
node T_30594 = and(T_30593, T_30592) @[rob.scala 484:56]
when T_30594 : @[rob.scala 485:10]
T_23706[12] <= UInt<1>("h00") @[rob.scala 486:24]
T_26182[UInt<4>("h0c")].inst <= UInt<32>("h04033") @[rob.scala 487:35]
skip @[rob.scala 485:10]
node T_30683 = eq(io.brinfo.mispredict, UInt<1>("h00")) @[rob.scala 489:40]
node T_30684 = and(io.brinfo.valid, T_30683) @[rob.scala 489:37]
node T_30685 = and(T_30684, T_30592) @[rob.scala 489:62]
node T_30687 = eq(T_30594, UInt<1>("h00")) @[rob.scala 485:10]
node T_30688 = and(T_30687, T_30685) @[rob.scala 490:10]
when T_30688 : @[rob.scala 490:10]
node T_30689 = not(io.brinfo.mask) @[rob.scala 492:46]
node T_30690 = and(T_26182[12].br_mask, T_30689) @[rob.scala 492:44]
T_26182[12].br_mask <= T_30690 @[rob.scala 492:32]
skip @[rob.scala 490:10]
node T_30691 = and(io.brinfo.mask, T_26182[13].br_mask) @[util.scala 45:52]
node T_30693 = neq(T_30691, UInt<1>("h00")) @[util.scala 45:60]
node T_30694 = and(T_23706[13], T_30693) @[rob.scala 481:39]
node T_30695 = and(io.brinfo.valid, io.brinfo.mispredict) @[rob.scala 484:32]
node T_30696 = and(T_30695, T_30694) @[rob.scala 484:56]
when T_30696 : @[rob.scala 485:10]
T_23706[13] <= UInt<1>("h00") @[rob.scala 486:24]
T_26182[UInt<4>("h0d")].inst <= UInt<32>("h04033") @[rob.scala 487:35]
skip @[rob.scala 485:10]
node T_30785 = eq(io.brinfo.mispredict, UInt<1>("h00")) @[rob.scala 489:40]
node T_30786 = and(io.brinfo.valid, T_30785) @[rob.scala 489:37]
node T_30787 = and(T_30786, T_30694) @[rob.scala 489:62]
node T_30789 = eq(T_30696, UInt<1>("h00")) @[rob.scala 485:10]
node T_30790 = and(T_30789, T_30787) @[rob.scala 490:10]
when T_30790 : @[rob.scala 490:10]
node T_30791 = not(io.brinfo.mask) @[rob.scala 492:46]
node T_30792 = and(T_26182[13].br_mask, T_30791) @[rob.scala 492:44]
T_26182[13].br_mask <= T_30792 @[rob.scala 492:32]
skip @[rob.scala 490:10]
node T_30793 = and(io.brinfo.mask, T_26182[14].br_mask) @[util.scala 45:52]
node T_30795 = neq(T_30793, UInt<1>("h00")) @[util.scala 45:60]
node T_30796 = and(T_23706[14], T_30795) @[rob.scala 481:39]
node T_30797 = and(io.brinfo.valid, io.brinfo.mispredict) @[rob.scala 484:32]
node T_30798 = and(T_30797, T_30796) @[rob.scala 484:56]
when T_30798 : @[rob.scala 485:10]
T_23706[14] <= UInt<1>("h00") @[rob.scala 486:24]
T_26182[UInt<4>("h0e")].inst <= UInt<32>("h04033") @[rob.scala 487:35]
skip @[rob.scala 485:10]
node T_30887 = eq(io.brinfo.mispredict, UInt<1>("h00")) @[rob.scala 489:40]
node T_30888 = and(io.brinfo.valid, T_30887) @[rob.scala 489:37]
node T_30889 = and(T_30888, T_30796) @[rob.scala 489:62]
node T_30891 = eq(T_30798, UInt<1>("h00")) @[rob.scala 485:10]
node T_30892 = and(T_30891, T_30889) @[rob.scala 490:10]
when T_30892 : @[rob.scala 490:10]
node T_30893 = not(io.brinfo.mask) @[rob.scala 492:46]
node T_30894 = and(T_26182[14].br_mask, T_30893) @[rob.scala 492:44]
T_26182[14].br_mask <= T_30894 @[rob.scala 492:32]
skip @[rob.scala 490:10]
node T_30895 = and(io.brinfo.mask, T_26182[15].br_mask) @[util.scala 45:52]
node T_30897 = neq(T_30895, UInt<1>("h00")) @[util.scala 45:60]
node T_30898 = and(T_23706[15], T_30897) @[rob.scala 481:39]
node T_30899 = and(io.brinfo.valid, io.brinfo.mispredict) @[rob.scala 484:32]
node T_30900 = and(T_30899, T_30898) @[rob.scala 484:56]
when T_30900 : @[rob.scala 485:10]
T_23706[15] <= UInt<1>("h00") @[rob.scala 486:24]
T_26182[UInt<4>("h0f")].inst <= UInt<32>("h04033") @[rob.scala 487:35]
skip @[rob.scala 485:10]
node T_30989 = eq(io.brinfo.mispredict, UInt<1>("h00")) @[rob.scala 489:40]
node T_30990 = and(io.brinfo.valid, T_30989) @[rob.scala 489:37]
node T_30991 = and(T_30990, T_30898) @[rob.scala 489:62]
node T_30993 = eq(T_30900, UInt<1>("h00")) @[rob.scala 485:10]
node T_30994 = and(T_30993, T_30991) @[rob.scala 490:10]
when T_30994 : @[rob.scala 490:10]
node T_30995 = not(io.brinfo.mask) @[rob.scala 492:46]
node T_30996 = and(T_26182[15].br_mask, T_30995) @[rob.scala 492:44]
T_26182[15].br_mask <= T_30996 @[rob.scala 492:32]
skip @[rob.scala 490:10]
node T_30997 = and(io.brinfo.mask, T_26182[16].br_mask) @[util.scala 45:52]
node T_30999 = neq(T_30997, UInt<1>("h00")) @[util.scala 45:60]
node T_31000 = and(T_23706[16], T_30999) @[rob.scala 481:39]
node T_31001 = and(io.brinfo.valid, io.brinfo.mispredict) @[rob.scala 484:32]
node T_31002 = and(T_31001, T_31000) @[rob.scala 484:56]
when T_31002 : @[rob.scala 485:10]
T_23706[16] <= UInt<1>("h00") @[rob.scala 486:24]
T_26182[UInt<5>("h010")].inst <= UInt<32>("h04033") @[rob.scala 487:35]
skip @[rob.scala 485:10]
node T_31091 = eq(io.brinfo.mispredict, UInt<1>("h00")) @[rob.scala 489:40]
node T_31092 = and(io.brinfo.valid, T_31091) @[rob.scala 489:37]
node T_31093 = and(T_31092, T_31000) @[rob.scala 489:62]
node T_31095 = eq(T_31002, UInt<1>("h00")) @[rob.scala 485:10]
node T_31096 = and(T_31095, T_31093) @[rob.scala 490:10]
when T_31096 : @[rob.scala 490:10]
node T_31097 = not(io.brinfo.mask) @[rob.scala 492:46]
node T_31098 = and(T_26182[16].br_mask, T_31097) @[rob.scala 492:44]
T_26182[16].br_mask <= T_31098 @[rob.scala 492:32]
skip @[rob.scala 490:10]
node T_31099 = and(io.brinfo.mask, T_26182[17].br_mask) @[util.scala 45:52]
node T_31101 = neq(T_31099, UInt<1>("h00")) @[util.scala 45:60]
node T_31102 = and(T_23706[17], T_31101) @[rob.scala 481:39]
node T_31103 = and(io.brinfo.valid, io.brinfo.mispredict) @[rob.scala 484:32]
node T_31104 = and(T_31103, T_31102) @[rob.scala 484:56]
when T_31104 : @[rob.scala 485:10]
T_23706[17] <= UInt<1>("h00") @[rob.scala 486:24]
T_26182[UInt<5>("h011")].inst <= UInt<32>("h04033") @[rob.scala 487:35]
skip @[rob.scala 485:10]
node T_31193 = eq(io.brinfo.mispredict, UInt<1>("h00")) @[rob.scala 489:40]
node T_31194 = and(io.brinfo.valid, T_31193) @[rob.scala 489:37]
node T_31195 = and(T_31194, T_31102) @[rob.scala 489:62]
node T_31197 = eq(T_31104, UInt<1>("h00")) @[rob.scala 485:10]
node T_31198 = and(T_31197, T_31195) @[rob.scala 490:10]
when T_31198 : @[rob.scala 490:10]
node T_31199 = not(io.brinfo.mask) @[rob.scala 492:46]
node T_31200 = and(T_26182[17].br_mask, T_31199) @[rob.scala 492:44]
T_26182[17].br_mask <= T_31200 @[rob.scala 492:32]
skip @[rob.scala 490:10]
node T_31201 = and(io.brinfo.mask, T_26182[18].br_mask) @[util.scala 45:52]
node T_31203 = neq(T_31201, UInt<1>("h00")) @[util.scala 45:60]
node T_31204 = and(T_23706[18], T_31203) @[rob.scala 481:39]
node T_31205 = and(io.brinfo.valid, io.brinfo.mispredict) @[rob.scala 484:32]
node T_31206 = and(T_31205, T_31204) @[rob.scala 484:56]
when T_31206 : @[rob.scala 485:10]
T_23706[18] <= UInt<1>("h00") @[rob.scala 486:24]
T_26182[UInt<5>("h012")].inst <= UInt<32>("h04033") @[rob.scala 487:35]
skip @[rob.scala 485:10]
node T_31295 = eq(io.brinfo.mispredict, UInt<1>("h00")) @[rob.scala 489:40]
node T_31296 = and(io.brinfo.valid, T_31295) @[rob.scala 489:37]
node T_31297 = and(T_31296, T_31204) @[rob.scala 489:62]
node T_31299 = eq(T_31206, UInt<1>("h00")) @[rob.scala 485:10]
node T_31300 = and(T_31299, T_31297) @[rob.scala 490:10]
when T_31300 : @[rob.scala 490:10]
node T_31301 = not(io.brinfo.mask) @[rob.scala 492:46]
node T_31302 = and(T_26182[18].br_mask, T_31301) @[rob.scala 492:44]
T_26182[18].br_mask <= T_31302 @[rob.scala 492:32]
skip @[rob.scala 490:10]
node T_31303 = and(io.brinfo.mask, T_26182[19].br_mask) @[util.scala 45:52]
node T_31305 = neq(T_31303, UInt<1>("h00")) @[util.scala 45:60]
node T_31306 = and(T_23706[19], T_31305) @[rob.scala 481:39]
node T_31307 = and(io.brinfo.valid, io.brinfo.mispredict) @[rob.scala 484:32]
node T_31308 = and(T_31307, T_31306) @[rob.scala 484:56]
when T_31308 : @[rob.scala 485:10]
T_23706[19] <= UInt<1>("h00") @[rob.scala 486:24]
T_26182[UInt<5>("h013")].inst <= UInt<32>("h04033") @[rob.scala 487:35]
skip @[rob.scala 485:10]
node T_31397 = eq(io.brinfo.mispredict, UInt<1>("h00")) @[rob.scala 489:40]
node T_31398 = and(io.brinfo.valid, T_31397) @[rob.scala 489:37]
node T_31399 = and(T_31398, T_31306) @[rob.scala 489:62]
node T_31401 = eq(T_31308, UInt<1>("h00")) @[rob.scala 485:10]
node T_31402 = and(T_31401, T_31399) @[rob.scala 490:10]
when T_31402 : @[rob.scala 490:10]
node T_31403 = not(io.brinfo.mask) @[rob.scala 492:46]
node T_31404 = and(T_26182[19].br_mask, T_31403) @[rob.scala 492:44]
T_26182[19].br_mask <= T_31404 @[rob.scala 492:32]
skip @[rob.scala 490:10]
node T_31405 = and(io.brinfo.mask, T_26182[20].br_mask) @[util.scala 45:52]
node T_31407 = neq(T_31405, UInt<1>("h00")) @[util.scala 45:60]
node T_31408 = and(T_23706[20], T_31407) @[rob.scala 481:39]
node T_31409 = and(io.brinfo.valid, io.brinfo.mispredict) @[rob.scala 484:32]
node T_31410 = and(T_31409, T_31408) @[rob.scala 484:56]
when T_31410 : @[rob.scala 485:10]
T_23706[20] <= UInt<1>("h00") @[rob.scala 486:24]
T_26182[UInt<5>("h014")].inst <= UInt<32>("h04033") @[rob.scala 487:35]
skip @[rob.scala 485:10]
node T_31499 = eq(io.brinfo.mispredict, UInt<1>("h00")) @[rob.scala 489:40]
node T_31500 = and(io.brinfo.valid, T_31499) @[rob.scala 489:37]
node T_31501 = and(T_31500, T_31408) @[rob.scala 489:62]
node T_31503 = eq(T_31410, UInt<1>("h00")) @[rob.scala 485:10]
node T_31504 = and(T_31503, T_31501) @[rob.scala 490:10]
when T_31504 : @[rob.scala 490:10]
node T_31505 = not(io.brinfo.mask) @[rob.scala 492:46]
node T_31506 = and(T_26182[20].br_mask, T_31505) @[rob.scala 492:44]
T_26182[20].br_mask <= T_31506 @[rob.scala 492:32]
skip @[rob.scala 490:10]
node T_31507 = and(io.brinfo.mask, T_26182[21].br_mask) @[util.scala 45:52]
node T_31509 = neq(T_31507, UInt<1>("h00")) @[util.scala 45:60]
node T_31510 = and(T_23706[21], T_31509) @[rob.scala 481:39]
node T_31511 = and(io.brinfo.valid, io.brinfo.mispredict) @[rob.scala 484:32]
node T_31512 = and(T_31511, T_31510) @[rob.scala 484:56]
when T_31512 : @[rob.scala 485:10]
T_23706[21] <= UInt<1>("h00") @[rob.scala 486:24]
T_26182[UInt<5>("h015")].inst <= UInt<32>("h04033") @[rob.scala 487:35]
skip @[rob.scala 485:10]
node T_31601 = eq(io.brinfo.mispredict, UInt<1>("h00")) @[rob.scala 489:40]
node T_31602 = and(io.brinfo.valid, T_31601) @[rob.scala 489:37]
node T_31603 = and(T_31602, T_31510) @[rob.scala 489:62]
node T_31605 = eq(T_31512, UInt<1>("h00")) @[rob.scala 485:10]
node T_31606 = and(T_31605, T_31603) @[rob.scala 490:10]
when T_31606 : @[rob.scala 490:10]
node T_31607 = not(io.brinfo.mask) @[rob.scala 492:46]
node T_31608 = and(T_26182[21].br_mask, T_31607) @[rob.scala 492:44]
T_26182[21].br_mask <= T_31608 @[rob.scala 492:32]
skip @[rob.scala 490:10]
node T_31609 = and(io.brinfo.mask, T_26182[22].br_mask) @[util.scala 45:52]
node T_31611 = neq(T_31609, UInt<1>("h00")) @[util.scala 45:60]
node T_31612 = and(T_23706[22], T_31611) @[rob.scala 481:39]
node T_31613 = and(io.brinfo.valid, io.brinfo.mispredict) @[rob.scala 484:32]
node T_31614 = and(T_31613, T_31612) @[rob.scala 484:56]
when T_31614 : @[rob.scala 485:10]
T_23706[22] <= UInt<1>("h00") @[rob.scala 486:24]
T_26182[UInt<5>("h016")].inst <= UInt<32>("h04033") @[rob.scala 487:35]
skip @[rob.scala 485:10]
node T_31703 = eq(io.brinfo.mispredict, UInt<1>("h00")) @[rob.scala 489:40]
node T_31704 = and(io.brinfo.valid, T_31703) @[rob.scala 489:37]
node T_31705 = and(T_31704, T_31612) @[rob.scala 489:62]
node T_31707 = eq(T_31614, UInt<1>("h00")) @[rob.scala 485:10]
node T_31708 = and(T_31707, T_31705) @[rob.scala 490:10]
when T_31708 : @[rob.scala 490:10]
node T_31709 = not(io.brinfo.mask) @[rob.scala 492:46]
node T_31710 = and(T_26182[22].br_mask, T_31709) @[rob.scala 492:44]
T_26182[22].br_mask <= T_31710 @[rob.scala 492:32]
skip @[rob.scala 490:10]
node T_31711 = and(io.brinfo.mask, T_26182[23].br_mask) @[util.scala 45:52]
node T_31713 = neq(T_31711, UInt<1>("h00")) @[util.scala 45:60]
node T_31714 = and(T_23706[23], T_31713) @[rob.scala 481:39]
node T_31715 = and(io.brinfo.valid, io.brinfo.mispredict) @[rob.scala 484:32]
node T_31716 = and(T_31715, T_31714) @[rob.scala 484:56]
when T_31716 : @[rob.scala 485:10]
T_23706[23] <= UInt<1>("h00") @[rob.scala 486:24]
T_26182[UInt<5>("h017")].inst <= UInt<32>("h04033") @[rob.scala 487:35]
skip @[rob.scala 485:10]
node T_31805 = eq(io.brinfo.mispredict, UInt<1>("h00")) @[rob.scala 489:40]
node T_31806 = and(io.brinfo.valid, T_31805) @[rob.scala 489:37]
node T_31807 = and(T_31806, T_31714) @[rob.scala 489:62]
node T_31809 = eq(T_31716, UInt<1>("h00")) @[rob.scala 485:10]
node T_31810 = and(T_31809, T_31807) @[rob.scala 490:10]
when T_31810 : @[rob.scala 490:10]
node T_31811 = not(io.brinfo.mask) @[rob.scala 492:46]
node T_31812 = and(T_26182[23].br_mask, T_31811) @[rob.scala 492:44]
T_26182[23].br_mask <= T_31812 @[rob.scala 492:32]
skip @[rob.scala 490:10]
when will_commit[0] : @[rob.scala 499:7]
T_23706[rob_head] <= UInt<1>("h00") @[rob.scala 500:28]
skip @[rob.scala 499:7]
rob_head_vals[0] <= T_23706[rob_head] @[rob.scala 505:28]
infer mport T_31814 = T_28314[rob_head], clk
rob_head_fflags[0] <= T_31814 @[rob.scala 506:28]
rob_head_is_store[0] <= T_26182[rob_head].is_store @[rob.scala 507:28]
rob_head_is_load[0] <= T_26182[rob_head].is_load @[rob.scala 508:28]
node T_31986 = dshr(io.get_pc.rob_idx, UInt<1>("h01")) @[rob.scala 222:27]
node T_31988 = eq(T_31986, UInt<5>("h017")) @[util.scala 75:28]
node T_31991 = add(T_31986, UInt<1>("h01")) @[util.scala 76:35]
node T_31992 = tail(T_31991, 1) @[util.scala 76:35]
node T_31993 = mux(T_31988, UInt<1>("h00"), T_31992) @[util.scala 76:13]
rob_brt_vals[0] <= T_23706[T_31993] @[rob.scala 509:28]
when will_commit[0] : @[rob.scala 514:7]
T_26182[rob_head].inst <= UInt<32>("h04033") @[rob.scala 515:33]
skip @[rob.scala 514:7]
node T_32079 = eq(rob_state, UInt<2>("h02")) @[rob.scala 517:28]
node T_32081 = eq(will_commit[0], UInt<1>("h00")) @[rob.scala 514:7]
node T_32082 = and(T_32081, T_32079) @[rob.scala 518:7]
when T_32082 : @[rob.scala 518:7]
T_26182[rob_tail].inst <= UInt<32>("h04033") @[rob.scala 519:33]
skip @[rob.scala 518:7]
node T_32168 = bits(io.wb_resps[0].bits.uop.rob_idx, 0, 0) @[rob.scala 227:38]
node T_32170 = eq(T_32168, UInt<1>("h00")) @[rob.scala 331:55]
node T_32171 = and(io.debug_wb_valids[0], T_32170) @[rob.scala 529:38]
when T_32171 : @[rob.scala 530:10]
node T_32173 = dshr(io.wb_resps[0].bits.uop.rob_idx, UInt<1>("h01")) @[rob.scala 222:27]
T_26182[T_32173].debug_wdata <= io.debug_wb_wdata[0] @[rob.scala 531:53]
skip @[rob.scala 530:10]
node T_32260 = dshr(io.wb_resps[0].bits.uop.rob_idx, UInt<1>("h01")) @[rob.scala 222:27]
node T_32346 = bits(io.wb_resps[0].bits.uop.rob_idx, 0, 0) @[rob.scala 227:38]
node T_32348 = eq(T_32346, UInt<1>("h00")) @[rob.scala 331:55]
node T_32349 = and(io.wb_resps[0].valid, T_32348) @[rob.scala 535:41]
node T_32351 = dshr(io.wb_resps[0].bits.uop.rob_idx, UInt<1>("h01")) @[rob.scala 222:27]
node T_32353 = eq(T_23706[T_32351], UInt<1>("h00")) @[rob.scala 536:22]
node T_32354 = and(T_32349, T_32353) @[rob.scala 535:75]
node T_32356 = eq(T_32354, UInt<1>("h00")) @[rob.scala 535:18]
node T_32357 = or(T_32356, reset) @[rob.scala 535:17]
node T_32359 = eq(T_32357, UInt<1>("h00")) @[rob.scala 535:17]
when T_32359 : @[rob.scala 535:17]
printf(clk, UInt<1>(1), "Assertion failed: [ROB] writeback occurred to an invalid ROB entry.\n at rob.scala:535 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\n") @[rob.scala 535:17]
stop(clk, UInt<1>(1), 1) @[rob.scala 535:17]
skip @[rob.scala 535:17]
node T_32360 = bits(io.wb_resps[0].bits.uop.rob_idx, 0, 0) @[rob.scala 227:38]
node T_32362 = eq(T_32360, UInt<1>("h00")) @[rob.scala 331:55]
node T_32363 = and(io.wb_resps[0].valid, T_32362) @[rob.scala 538:41]
node T_32364 = and(T_32363, T_26182[T_32260].ldst_val) @[rob.scala 538:75]
node T_32365 = neq(T_26182[T_32260].pdst, io.wb_resps[0].bits.uop.pdst) @[rob.scala 539:54]
node T_32366 = and(T_32364, T_32365) @[rob.scala 539:37]
node T_32368 = eq(T_32366, UInt<1>("h00")) @[rob.scala 538:18]
node T_32369 = or(T_32368, reset) @[rob.scala 538:17]
node T_32371 = eq(T_32369, UInt<1>("h00")) @[rob.scala 538:17]
when T_32371 : @[rob.scala 538:17]
printf(clk, UInt<1>(1), "Assertion failed: [ROB] writeback occurred to the wrong pdst.\n at rob.scala:538 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\n") @[rob.scala 538:17]
stop(clk, UInt<1>(1), 1) @[rob.scala 538:17]
skip @[rob.scala 538:17]
node T_32372 = bits(io.wb_resps[1].bits.uop.rob_idx, 0, 0) @[rob.scala 227:38]
node T_32374 = eq(T_32372, UInt<1>("h00")) @[rob.scala 331:55]
node T_32375 = and(io.debug_wb_valids[1], T_32374) @[rob.scala 529:38]
when T_32375 : @[rob.scala 530:10]
node T_32377 = dshr(io.wb_resps[1].bits.uop.rob_idx, UInt<1>("h01")) @[rob.scala 222:27]
T_26182[T_32377].debug_wdata <= io.debug_wb_wdata[1] @[rob.scala 531:53]
skip @[rob.scala 530:10]
node T_32464 = dshr(io.wb_resps[1].bits.uop.rob_idx, UInt<1>("h01")) @[rob.scala 222:27]
node T_32550 = bits(io.wb_resps[1].bits.uop.rob_idx, 0, 0) @[rob.scala 227:38]
node T_32552 = eq(T_32550, UInt<1>("h00")) @[rob.scala 331:55]
node T_32553 = and(io.wb_resps[1].valid, T_32552) @[rob.scala 535:41]
node T_32555 = dshr(io.wb_resps[1].bits.uop.rob_idx, UInt<1>("h01")) @[rob.scala 222:27]
node T_32557 = eq(T_23706[T_32555], UInt<1>("h00")) @[rob.scala 536:22]
node T_32558 = and(T_32553, T_32557) @[rob.scala 535:75]
node T_32560 = eq(T_32558, UInt<1>("h00")) @[rob.scala 535:18]
node T_32561 = or(T_32560, reset) @[rob.scala 535:17]
node T_32563 = eq(T_32561, UInt<1>("h00")) @[rob.scala 535:17]
when T_32563 : @[rob.scala 535:17]
printf(clk, UInt<1>(1), "Assertion failed: [ROB] writeback occurred to an invalid ROB entry.\n at rob.scala:535 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\n") @[rob.scala 535:17]
stop(clk, UInt<1>(1), 1) @[rob.scala 535:17]
skip @[rob.scala 535:17]
node T_32564 = bits(io.wb_resps[1].bits.uop.rob_idx, 0, 0) @[rob.scala 227:38]
node T_32566 = eq(T_32564, UInt<1>("h00")) @[rob.scala 331:55]
node T_32567 = and(io.wb_resps[1].valid, T_32566) @[rob.scala 538:41]
node T_32568 = and(T_32567, T_26182[T_32464].ldst_val) @[rob.scala 538:75]
node T_32569 = neq(T_26182[T_32464].pdst, io.wb_resps[1].bits.uop.pdst) @[rob.scala 539:54]
node T_32570 = and(T_32568, T_32569) @[rob.scala 539:37]
node T_32572 = eq(T_32570, UInt<1>("h00")) @[rob.scala 538:18]
node T_32573 = or(T_32572, reset) @[rob.scala 538:17]
node T_32575 = eq(T_32573, UInt<1>("h00")) @[rob.scala 538:17]
when T_32575 : @[rob.scala 538:17]
printf(clk, UInt<1>(1), "Assertion failed: [ROB] writeback occurred to the wrong pdst.\n at rob.scala:538 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\n") @[rob.scala 538:17]
stop(clk, UInt<1>(1), 1) @[rob.scala 538:17]
skip @[rob.scala 538:17]
node T_32576 = bits(io.wb_resps[2].bits.uop.rob_idx, 0, 0) @[rob.scala 227:38]
node T_32578 = eq(T_32576, UInt<1>("h00")) @[rob.scala 331:55]
node T_32579 = and(io.debug_wb_valids[2], T_32578) @[rob.scala 529:38]
when T_32579 : @[rob.scala 530:10]
node T_32581 = dshr(io.wb_resps[2].bits.uop.rob_idx, UInt<1>("h01")) @[rob.scala 222:27]
T_26182[T_32581].debug_wdata <= io.debug_wb_wdata[2] @[rob.scala 531:53]
skip @[rob.scala 530:10]
node T_32668 = dshr(io.wb_resps[2].bits.uop.rob_idx, UInt<1>("h01")) @[rob.scala 222:27]
node T_32754 = bits(io.wb_resps[2].bits.uop.rob_idx, 0, 0) @[rob.scala 227:38]
node T_32756 = eq(T_32754, UInt<1>("h00")) @[rob.scala 331:55]
node T_32757 = and(io.wb_resps[2].valid, T_32756) @[rob.scala 535:41]
node T_32759 = dshr(io.wb_resps[2].bits.uop.rob_idx, UInt<1>("h01")) @[rob.scala 222:27]
node T_32761 = eq(T_23706[T_32759], UInt<1>("h00")) @[rob.scala 536:22]
node T_32762 = and(T_32757, T_32761) @[rob.scala 535:75]
node T_32764 = eq(T_32762, UInt<1>("h00")) @[rob.scala 535:18]
node T_32765 = or(T_32764, reset) @[rob.scala 535:17]
node T_32767 = eq(T_32765, UInt<1>("h00")) @[rob.scala 535:17]
when T_32767 : @[rob.scala 535:17]
printf(clk, UInt<1>(1), "Assertion failed: [ROB] writeback occurred to an invalid ROB entry.\n at rob.scala:535 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\n") @[rob.scala 535:17]
stop(clk, UInt<1>(1), 1) @[rob.scala 535:17]
skip @[rob.scala 535:17]
node T_32768 = bits(io.wb_resps[2].bits.uop.rob_idx, 0, 0) @[rob.scala 227:38]
node T_32770 = eq(T_32768, UInt<1>("h00")) @[rob.scala 331:55]
node T_32771 = and(io.wb_resps[2].valid, T_32770) @[rob.scala 538:41]
node T_32772 = and(T_32771, T_26182[T_32668].ldst_val) @[rob.scala 538:75]
node T_32773 = neq(T_26182[T_32668].pdst, io.wb_resps[2].bits.uop.pdst) @[rob.scala 539:54]
node T_32774 = and(T_32772, T_32773) @[rob.scala 539:37]
node T_32776 = eq(T_32774, UInt<1>("h00")) @[rob.scala 538:18]
node T_32777 = or(T_32776, reset) @[rob.scala 538:17]
node T_32779 = eq(T_32777, UInt<1>("h00")) @[rob.scala 538:17]
when T_32779 : @[rob.scala 538:17]
printf(clk, UInt<1>(1), "Assertion failed: [ROB] writeback occurred to the wrong pdst.\n at rob.scala:538 assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&\n") @[rob.scala 538:17]
stop(clk, UInt<1>(1), 1) @[rob.scala 538:17]
skip @[rob.scala 538:17]
io.com_uops[0].debug_wdata <= T_26182[rob_head].debug_wdata @[rob.scala 542:34]
debug_entry[0].valid <= T_23706[0] @[rob.scala 551:44]
infer mport T_32866 = T_23710[UInt<1>("h00")], clk
debug_entry[0].busy <= T_32866 @[rob.scala 552:43]
debug_entry[0].uop <- T_26182[UInt<1>("h00")] @[rob.scala 553:42]
wire T_32955 : UInt<64> @[rob.scala 899:26]
T_32955 is invalid @[rob.scala 899:26]
node T_32957 = dshr(UInt<5>("h00"), UInt<1>("h01")) @[rob.scala 900:33]
infer mport T_32958 = T_23555[T_32957], clk
node T_32960 = dshl(T_32958, UInt<2>("h03")) @[rob.scala 900:45]
T_32955 <= T_32960 @[rob.scala 900:16]
when UInt<1>("h00") : @[rob.scala 903:10]
node T_32963 = dshr(UInt<5>("h00"), UInt<1>("h01")) @[rob.scala 904:36]
infer mport T_32964 = T_23558[T_32963], clk
node T_32966 = dshl(T_32964, UInt<2>("h03")) @[rob.scala 904:48]
T_32955 <= T_32966 @[rob.scala 904:19]
skip @[rob.scala 903:10]
node T_32967 = bits(T_32955, 39, 0) @[rob.scala 906:20]
node T_32968 = bits(T_32967, 39, 39) @[util.scala 114:43]
node T_32969 = bits(T_32968, 0, 0) @[Bitwise.scala 33:15]
node T_32972 = mux(T_32969, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 33:12]
node T_32973 = cat(T_32972, T_32967) @[Cat.scala 20:58]
node T_32975 = add(T_32973, UInt<1>("h00")) @[rob.scala 554:94]
node T_32976 = tail(T_32975, 1) @[rob.scala 554:94]
debug_entry[0].uop.pc <= T_32976 @[rob.scala 554:45]
infer mport T_32978 = T_28311[UInt<1>("h00")], clk
debug_entry[0].exception <= T_32978 @[rob.scala 555:48]
debug_entry[2].valid <= T_23706[1] @[rob.scala 551:44]
infer mport T_32980 = T_23710[UInt<1>("h01")], clk
debug_entry[2].busy <= T_32980 @[rob.scala 552:43]
debug_entry[2].uop <- T_26182[UInt<1>("h01")] @[rob.scala 553:42]
wire T_33069 : UInt<64> @[rob.scala 899:26]
T_33069 is invalid @[rob.scala 899:26]
node T_33071 = dshr(UInt<5>("h01"), UInt<1>("h01")) @[rob.scala 900:33]
infer mport T_33072 = T_23555[T_33071], clk
node T_33074 = dshl(T_33072, UInt<2>("h03")) @[rob.scala 900:45]
T_33069 <= T_33074 @[rob.scala 900:16]
when UInt<1>("h01") : @[rob.scala 903:10]
node T_33077 = dshr(UInt<5>("h01"), UInt<1>("h01")) @[rob.scala 904:36]
infer mport T_33078 = T_23558[T_33077], clk
node T_33080 = dshl(T_33078, UInt<2>("h03")) @[rob.scala 904:48]
T_33069 <= T_33080 @[rob.scala 904:19]
skip @[rob.scala 903:10]
node T_33081 = bits(T_33069, 39, 0) @[rob.scala 906:20]
node T_33082 = bits(T_33081, 39, 39) @[util.scala 114:43]
node T_33083 = bits(T_33082, 0, 0) @[Bitwise.scala 33:15]
node T_33086 = mux(T_33083, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 33:12]
node T_33087 = cat(T_33086, T_33081) @[Cat.scala 20:58]
node T_33089 = add(T_33087, UInt<1>("h00")) @[rob.scala 554:94]
node T_33090 = tail(T_33089, 1) @[rob.scala 554:94]
debug_entry[2].uop.pc <= T_33090 @[rob.scala 554:45]
infer mport T_33092 = T_28311[UInt<1>("h01")], clk
debug_entry[2].exception <= T_33092 @[rob.scala 555:48]
debug_entry[4].valid <= T_23706[2] @[rob.scala 551:44]
infer mport T_33094 = T_23710[UInt<2>("h02")], clk
debug_entry[4].busy <= T_33094 @[rob.scala 552:43]
debug_entry[4].uop <- T_26182[UInt<2>("h02")] @[rob.scala 553:42]
wire T_33183 : UInt<64> @[rob.scala 899:26]
T_33183 is invalid @[rob.scala 899:26]
node T_33185 = dshr(UInt<5>("h02"), UInt<1>("h01")) @[rob.scala 900:33]
infer mport T_33186 = T_23555[T_33185], clk
node T_33188 = dshl(T_33186, UInt<2>("h03")) @[rob.scala 900:45]
T_33183 <= T_33188 @[rob.scala 900:16]
when UInt<1>("h00") : @[rob.scala 903:10]
node T_33191 = dshr(UInt<5>("h02"), UInt<1>("h01")) @[rob.scala 904:36]
infer mport T_33192 = T_23558[T_33191], clk
node T_33194 = dshl(T_33192, UInt<2>("h03")) @[rob.scala 904:48]
T_33183 <= T_33194 @[rob.scala 904:19]
skip @[rob.scala 903:10]
node T_33195 = bits(T_33183, 39, 0) @[rob.scala 906:20]
node T_33196 = bits(T_33195, 39, 39) @[util.scala 114:43]
node T_33197 = bits(T_33196, 0, 0) @[Bitwise.scala 33:15]
node T_33200 = mux(T_33197, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 33:12]
node T_33201 = cat(T_33200, T_33195) @[Cat.scala 20:58]
node T_33203 = add(T_33201, UInt<1>("h00")) @[rob.scala 554:94]
node T_33204 = tail(T_33203, 1) @[rob.scala 554:94]
debug_entry[4].uop.pc <= T_33204 @[rob.scala 554:45]
infer mport T_33206 = T_28311[UInt<2>("h02")], clk
debug_entry[4].exception <= T_33206 @[rob.scala 555:48]
debug_entry[6].valid <= T_23706[3] @[rob.scala 551:44]
infer mport T_33208 = T_23710[UInt<2>("h03")], clk
debug_entry[6].busy <= T_33208 @[rob.scala 552:43]
debug_entry[6].uop <- T_26182[UInt<2>("h03")] @[rob.scala 553:42]
wire T_33297 : UInt<64> @[rob.scala 899:26]
T_33297 is invalid @[rob.scala 899:26]
node T_33299 = dshr(UInt<5>("h03"), UInt<1>("h01")) @[rob.scala 900:33]
infer mport T_33300 = T_23555[T_33299], clk
node T_33302 = dshl(T_33300, UInt<2>("h03")) @[rob.scala 900:45]
T_33297 <= T_33302 @[rob.scala 900:16]
when UInt<1>("h01") : @[rob.scala 903:10]
node T_33305 = dshr(UInt<5>("h03"), UInt<1>("h01")) @[rob.scala 904:36]
infer mport T_33306 = T_23558[T_33305], clk
node T_33308 = dshl(T_33306, UInt<2>("h03")) @[rob.scala 904:48]
T_33297 <= T_33308 @[rob.scala 904:19]
skip @[rob.scala 903:10]
node T_33309 = bits(T_33297, 39, 0) @[rob.scala 906:20]
node T_33310 = bits(T_33309, 39, 39) @[util.scala 114:43]
node T_33311 = bits(T_33310, 0, 0) @[Bitwise.scala 33:15]
node T_33314 = mux(T_33311, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 33:12]
node T_33315 = cat(T_33314, T_33309) @[Cat.scala 20:58]
node T_33317 = add(T_33315, UInt<1>("h00")) @[rob.scala 554:94]