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Formatter unable to recognize class instantiation with parameter override inside a struct/union #2184

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brendany1990 opened this issue May 22, 2024 · 0 comments
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formatter Verilog code formatter issues

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@brendany1990
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Version

v0.0-3648-g5ef1624a
Commit  2024-05-04
Built   2024-05-05T00:06:13Z

Test case

// Input to the formatter, preferably a reduced test case.
class fooClass#(parameter fooWidth);
    typedef struct packed {
        logic [fooWidth-1:0] fooLogic;
    } t;
endclass

typedef struct packed {
    fooClass#(.fooWidth(8))::t foo;
} foo_t;

Include any options or configuration used.

Actual output
Error from verible-verilog-format

test.sv:8:15: syntax error at token "."
test.sv:9:1: syntax error at token "}"

Include any possible diagnostic messages from the formatter.

Expected or suggested output
I was able to compile the test case via modelsim so I believe it should be syntactically valid. Just to note, one way to workaround this is to typedef the class instantiation

class fooClass#(parameter fooWidth);
    typedef struct packed {
        logic [fooWidth-1:0] fooLogic;
    } t;
endclass

typedef fooClass#(.fooWidth(8))::t _foo_t

typedef struct packed {
    _foo_t foo;
} foo_t;

Citations to published style guides would help.

@brendany1990 brendany1990 added the formatter Verilog code formatter issues label May 22, 2024
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Labels
formatter Verilog code formatter issues
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