The hardware/software codesign challenge for ECE4530 where we attempt to beat each other in speeding up SHA-1 and collision detection.
This project contains the following directories:
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archives: The project archives containing the Quartus information and the reference implementation.
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doc: Contains all of my documentation on my work through the project, serving as the basis for my report on the project.
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drawings: Contains my drawings of planned designs, which are not implemented in the exact manner I describe.
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img: Contains all images associated with my documentation such as screenshots of output from the code execution as well as my diagrams of how I attempted to optimize the design.
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src: The source code (both C and Verilog) that I wrote to optimize my design. My QSYS alterations are not found here, but can be found in the final submission archive located in the archives directory.