Adding sig gen module to docs

chiranthsiddappa · Apr 16, 2019 · e4a791a · e4a791a
1 parent ec71907
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diff --git a/docs/source/index.rst b/docs/source/index.rst
@@ -19,6 +19,7 @@ Welcome to CAF Verilog's documentation!
    dot_product
    io_helper
    quantizer
+   sig_gen
 
 
 Indices and tables

diff --git a/docs/source/sig_gen.rst b/docs/source/sig_gen.rst
@@ -0,0 +1,7 @@
+sig_gen
+=======
+
+.. automodule:: caf_verilog.sig_gen
+     :members:
+     :undoc-members:
+     :show-inheritance: