New timings matched with reference_buffer

src/capture_buffer.v

@@ -31,23 +31,26 @@ module capture_buffer #(parameter buffer_length = 10,
 
    initial begin
       s_axi_rready = 1'b0;
+      s_axi_rvalid = 1'b0;
       s_axi_wready = 1'b0;
       s_axi_bvalid = 1'b0;
    end
 
    always @(posedge clk) begin
-      m_r_axi_valid <= m_axi_rvalid & m_axi_rready;
-      r_addr_buffer <= m_axi_raddr;
+      m_r_axi_valid <= m_axi_rvalid;
+      if (m_axi_rvalid) begin
+         r_addr_buffer <= m_axi_raddr;
+      end
    end
 
    always @(posedge clk) begin
-      s_axi_rready <= 1'b1;
+      s_axi_rready <= m_axi_rready | ~s_axi_rvalid;
       if (m_r_axi_valid && (r_addr_buffer < buffer_length)) begin
          i <= buffer[r_addr_buffer][i_bits + q_bits - 1:q_bits];
          q <= buffer[r_addr_buffer][q_bits:0];
          s_axi_rvalid <= 1'b1;
       end
-      else begin
+      else if (m_axi_rready) begin
          s_axi_rvalid <= 1'b0;
       end
    end

src/capture_buffer_tb.v

@@ -34,8 +34,10 @@ module capture_buffer_tb();
       m_axi_waddr = 'd0;
       m_axi_wvalid = 1'b1;
       m_axi_wdata = buffer_values['d0];
-      @(posedge clk) m_axi_rvalid = 1'b1;
-      @(posedge clk) m_axi_rready = 1'b1;
+      @(posedge clk) begin
+         m_axi_rvalid = 1'b1;
+         m_axi_rready = 1'b1;
+      end // UNMATCHED !!
       @(posedge clk) m_axi_raddr = 'd1;
    end // initial begin