Incorrect vhdl generation for default value in blackbox

[BosJ]

The following code:

module Error where 

import CLaSH.Prelude

data Dat = Con Rec | Nop 
data Rec = Rec { testVec :: Vec 3 Bool } 

topEntity :: Dat -> Vec 3 Bool
topEntity x = testVec h where
    (Con h) = x

Is translated to:

entity topEntity_0 is
  port(x_i1      : in std_logic_vector(3 downto 0);
       bodyVar_o : out array_of_boolean(2 downto 0));
end;

architecture structural of topEntity_0 is
  signal ds1_0 : array_of_boolean(2 downto 0);
  signal h_1   : array_of_boolean(2 downto 0);
  signal ds_2  : array_of_boolean(2 downto 0);
begin
  ds1_0 <= ds_2;

  h_1 <= (fromSL(x_i1(2))
         ,fromSL(x_i1(1))
         ,fromSL(x_i1(0)));

  ds_2 <= h_1 when (x_i1(3 downto 3) = "0") else
          (others => '0');

  bodyVar_o <= ds1_0;
end;

type array_of_boolean is array (integer range <>) of boolean;

But the assignment to ds_2 should be:

  ds_2 <= h_1 when (x_i1(3 downto 3) = "0") else
          (others => false);

Workaround:

module Error where 

import CLaSH.Prelude

data Dat = Con Rec | Nop 
data Rec = Rec { testVec :: Vec 3 Bool } 

topEntity :: Dat -> Vec 3 Bool
topEntity x = case x of
        (Con h) -> testVec h
        _       -> undefined