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Fix typos

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1 parent b4b0e8a commit 8dbb9f84b45c91f448bdb71067b450014c2d4b64 @christiaanb committed Aug 31, 2009
Showing with 8 additions and 8 deletions.
  1. +7 −7 PolyAlu.hs
  2. +1 −1 reducer.lhs
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14 PolyAlu.hs
@@ -5,27 +5,27 @@ module Main where
import CLasH.HardwareTypes
import CLasH.Translator.Annotations
import qualified Prelude as P
-{-# LINE 51 "PolyAlu.lhs" #-}
+{-# LINE 52 "PolyAlu.lhs" #-}
type Op a = a -> a -> a
-{-# LINE 58 "PolyAlu.lhs" #-}
+type Opcode = Bit
+{-# LINE 60 "PolyAlu.lhs" #-}
type RegBank s a =
Vector (s :+: D1) a
type RegState s a =
State (RegBank s a)
-{-# LINE 66 "PolyAlu.lhs" #-}
+{-# LINE 68 "PolyAlu.lhs" #-}
type Word = SizedInt D12
-{-# LINE 85 "PolyAlu.lhs" #-}
-type Opcode = Bit
+{-# LINE 88 "PolyAlu.lhs" #-}
alu ::
Op a -> Op a ->
Opcode -> a -> a -> a
alu op1 op2 Low a b = op1 a b
alu op1 op2 High a b = op2 a b
-{-# LINE 108 "PolyAlu.lhs" #-}
+{-# LINE 110 "PolyAlu.lhs" #-}
registers ::
((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) => a -> RangedWord s ->
RangedWord s -> (RegState s a) -> (RegState s a, a )
-{-# LINE 116 "PolyAlu.lhs" #-}
+{-# LINE 118 "PolyAlu.lhs" #-}
registers data_in rdaddr wraddr (State mem) =
((State mem'), data_out)
where
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2 reducer.lhs
@@ -10,7 +10,7 @@
\column{0.5\textwidth}
\begin{itemize}
\item We implemented a reduction circuit in \clash{}\pause
- \item Simulated first Haskell. VHDL simulation results match\pause
+ \item Simulated in Haskell. VHDL simulation results match\pause
\item Synthesis completes without errors or warnings\pause
\item Around half speed of handcoded and optimized VHDL
\end{itemize}

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