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chsachinkumar/README.md

MasterHead

Hi 👋, I'm Chaudhary Sachin Kumar

A passionate ASIC_VLSI and web developer from India

Coding

chsachinkumar

  • 🔭 I’m currently working on ASIC_VLSI
  • 🌱 I’m currently learning C/JAVA/Python
  • 👯 I’m looking to collaborate on ASIC_VLSI_Projects
  • 💬 Ask me about ASIC_VLSI

Connect With Me:

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chsachinkumar

chsachinku2003

Connect with me:

chsachinku2003chaudhary sachin kumarchsachinku2003ch_sachin_2003

Languages and Tools:

Verilog Verilog xilinx python c java

chsachinkumar

chsachinkumar chsachinkumar

Pinned

  1. UART-Half-Duplex-Serial-Port-Module-Design UART-Half-Duplex-Serial-Port-Module-Design Public

    This repository contains an UART Half Duplex Serial Port Module Design

    Verilog 1