Merge pull request #35 from circuitgraph/dev

Update to 0.2.1

.github/workflows/python-package.yml

@@ -16,7 +16,7 @@ jobs:
     strategy:
       fail-fast: false
       matrix:
-        python-version: ["3.6", "3.7", "3.8", "3.9", "3.10"]
+        python-version: ["3.7", "3.8", "3.9", "3.10"]
 
     steps:
     - uses: actions/checkout@v2

.pre-commit-config.yaml

@@ -1,29 +1,30 @@
 repos:
   - repo: https://github.com/pre-commit/pre-commit-hooks
-    rev: v4.1.0
+    rev: v4.4.0
     hooks:
+    - id: check-ast
+    - id: check-docstring-first
+    - id: check-toml
+    - id: check-yaml
+    - id: end-of-file-fixer
+    - id: mixed-line-ending
+    - id: sort-simple-yaml
     - id: trailing-whitespace
-  - repo: https://github.com/pycqa/flake8
-    rev: 4.0.1
-    hooks:
-    - id: flake8
-      args: ["--select=E9,F63,F7,F82"]
   - repo: https://github.com/pycqa/isort
-    rev: 5.10.1
+    rev: 5.12.0
     hooks:
     - id: isort
       name: isort (python)
       args: ["--profile",  "black", "--skip", "__init__.py", "--filter-files"]
-  - repo: https://github.com/asottile/pyupgrade
-    rev: v2.31.0
-    hooks:
-    - id: pyupgrade
-      args: ["--py37-plus"]
   - repo: https://github.com/psf/black
-    rev: 19.10b0
+    rev: 23.3.0
     hooks:
       - id: black
-        language_version: python3
+  - repo: https://github.com/pycqa/flake8
+    rev: 6.0.0
+    hooks:
+    - id: flake8
+      args: ["--select=E9,F63,F7,F82"]
   - repo: https://github.com/myint/docformatter
     rev: v1.4
     hooks:

CHANGELOG.md

@@ -1,6 +1,25 @@
 # Changelog
 All notable changes to this project will be documented in this file.
 
+## [0.2.1] -
+### Fixed
+- Approximate model counting subprocess newlines and encoding
+- `set_type` docstring
+- `props.influence` docstring
+- Ternary transform for circuits with xor/xnor gates
+- `sat.construct_solver` works with newer versions of `python-sat`
+
+### Added
+- Generic flop blackbox
+- `insert_registers` transform
+- `limit_fanout` transform
+- `levelize` function
+
+### Changed
+- `sat.construct_solver` accepts a `pysat.Solver` class instead of a string for greater flexibility. If no solver is specified, `Cadical` (`Cadical153` for newer versions of `python-sat`) will be used.
+- Added `stretch` argument to Yosys `show` command for `cg.visualize`
+
+
 ## [0.2.0] - 2022-04-22
 ### Fixed
 - Visualization with BlackBoxes.

README.md

@@ -28,7 +28,7 @@ The documentation can be found [here](https://circuitgraph.github.io/circuitgrap
 
 ## Installation
 
-CircuitGraph requires Python3.6 or greater
+CircuitGraph requires Python3.7 or greater
 The easiest way to install is via PyPi:
 ```shell
 pip install circuitgraph

circuitgraph/__init__.py

@@ -23,6 +23,13 @@
     addable_types,
     supported_types,
 )
-from circuitgraph.io import dc_flops, from_file, from_lib, genus_flops, to_file
+from circuitgraph.io import (
+    generic_flop,
+    dc_flops,
+    from_file,
+    from_lib,
+    genus_flops,
+    to_file,
+)
 from circuitgraph.utils import lint, visualize
 from circuitgraph import logic, props, sat, tx, utils

circuitgraph/circuit.py

@@ -214,7 +214,7 @@ def copy(self):
 
     def set_type(self, ns, t):
         """
-        Return node(s) type(s).
+        Set the type of a node or nodes.
 
         Parameters
         ----------

circuitgraph/io.py

@@ -5,6 +5,8 @@
 from circuitgraph import BlackBox, Circuit
 from circuitgraph.parsing import fast_parse_verilog_netlist, parse_verilog_netlist
 
+generic_flop = BlackBox("ff", ["clk", "d"], ["q"])
+
 genus_flops = [
     BlackBox("flopd", ["CK", "D"], ["Q"]),
     BlackBox("fflopd", ["CK", "D"], ["Q"]),
@@ -98,7 +100,7 @@ def from_lib(name):
             the parsed circuit.
 
     """
-    bbs = [BlackBox("ff", ["CK", "D"], ["Q"])]
+    bbs = [BlackBox("ff", ["CK", "D"], ["Q"])] + genus_flops + dc_flops
     [path] = Path(__file__).parent.absolute().glob(f"netlists/{name}.*")
     return from_file(path, name, blackboxes=bbs)
 
@@ -335,7 +337,8 @@ def circuit_to_verilog(c, behavioral=False):
                         insts.append(f"assign {n} = {fanin}")
             else:
                 fanin = ", ".join(fanin)
-                insts.append(f"{c.type(n)} g_{len(insts)} " f"({n}, {fanin})")
+                gate_name = c.uid(f"g_{len(insts)}")
+                insts.append(f"{c.type(n)} {gate_name}({n}, {fanin})")
         elif c.type(n) in ["0", "1", "x"]:
             insts.append(f"assign {n} = 1'b{c.type(n)}")
             wires.append(n)