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Thanks very much for your response. During the first developing stage, I refer to avalon codes, so their coding styles look a little similar, but the data structrue and processing flow are quite different. We will release our ASIC and miner in around two months later. They will be more efficient mining devices, and be quite different from avalon chips and miners. In order to support our chips and devices, bitmain mode should be added. We hope our miner support UART, USB and LAN interfaces. The FT232 chip descriptor is built in the code, since our FPGA verication platform is based on this chip, but it is not proper. According to your comments, we will revise the codes and we hope to get more guide and opinions form you. Soon, when our miner is ready, we will send a set of them to you for the code optimiztion. By the way, could you give me your e-mail or other contact method? We hope to get more instruction from you. |
My email is in the readme and I am also on IRC, as per the readme. |
This submission provides support for AntMiner devices, including BitMain Multi Chain Mode and Single Chain Mode. According to your comments, we will revise the codes and we hope to get more guide and opinions form you. |
Please merge code with current master cgminer code. |
What is the status of this? Will it be merged in soon? Or is there more work to be done? If there is more work what needs to be done? |
The commit cannot be merged - since it is not based on the current git. |
See the comments. The code doesn't even apply at the moment. |
Bitmain Technologies Inc. is a new ASIC miner vendor. Our chip will be released in around two months later. In order to support our chip, bitmain mode is added in this version of codes.