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s390.ad
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//
// Copyright (c) 2017, 2021, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2017, 2020 SAP SE. All rights reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This code is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License version 2 only, as
// published by the Free Software Foundation.
//
// This code is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// version 2 for more details (a copy is included in the LICENSE file that
// accompanied this code).
//
// You should have received a copy of the GNU General Public License version
// 2 along with this work; if not, write to the Free Software Foundation,
// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
//
// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
// or visit www.oracle.com if you need additional information or have any
// questions.
//
// z/Architecture Architecture Description File
// Major contributions by AS, JL, LS.
//
// Following information is derived from private mail communication
// (Oct. 2011).
//
// General branch target alignment considerations
//
// z/Architecture does not imply a general branch target alignment requirement.
// There are side effects and side considerations, though, which may
// provide some performance benefit. These are:
// - Align branch target on octoword (32-byte) boundary
// On more recent models (from z9 on), I-fetch is done on a Octoword
// (32 bytes at a time) basis. To avoid I-fetching unnecessary
// instructions, branch targets should be 32-byte aligend. If this
// exact alingment cannot be achieved, having the branch target in
// the first doubleword still provides some benefit.
// - Avoid branch targets at the end of cache lines (> 64 bytes distance).
// Sequential instruction prefetching after the branch target starts
// immediately after having fetched the octoword containing the
// branch target. When I-fetching crosses a cache line, there may be
// a small stall. The worst case: the branch target (at the end of
// a cache line) is a L1 I-cache miss and the next line as well.
// Then, the entire target line must be filled first (to contine at the
// branch target). Only then can the next sequential line be filled.
// - Avoid multiple poorly predicted branches in a row.
//
//----------REGISTER DEFINITION BLOCK------------------------------------------
// This information is used by the matcher and the register allocator to
// describe individual registers and classes of registers within the target
// architecture.
register %{
//----------Architecture Description Register Definitions----------------------
// General Registers
// "reg_def" name (register save type, C convention save type,
// ideal register type, encoding);
//
// Register Save Types:
//
// NS = No-Save: The register allocator assumes that these registers
// can be used without saving upon entry to the method, &
// that they do not need to be saved at call sites.
//
// SOC = Save-On-Call: The register allocator assumes that these registers
// can be used without saving upon entry to the method,
// but that they must be saved at call sites.
//
// SOE = Save-On-Entry: The register allocator assumes that these registers
// must be saved before using them upon entry to the
// method, but they do not need to be saved at call sites.
//
// AS = Always-Save: The register allocator assumes that these registers
// must be saved before using them upon entry to the
// method, & that they must be saved at call sites.
//
// Ideal Register Type is used to determine how to save & restore a
// register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
// spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
//
// The encoding number is the actual bit-pattern placed into the opcodes.
// z/Architecture register definitions, based on the z/Architecture Principles
// of Operation, 5th Edition, September 2005, and z/Linux Elf ABI Supplement,
// 5th Edition, March 2001.
//
// For each 64-bit register we must define two registers: the register
// itself, e.g. Z_R3, and a corresponding virtual other (32-bit-)'half',
// e.g. Z_R3_H, which is needed by the allocator, but is not used
// for stores, loads, etc.
// Integer/Long Registers
// ----------------------------
// z/Architecture has 16 64-bit integer registers.
// types: v = volatile, nv = non-volatile, s = system
reg_def Z_R0 (SOC, SOC, Op_RegI, 0, Z_R0->as_VMReg()); // v scratch1
reg_def Z_R0_H (SOC, SOC, Op_RegI, 99, Z_R0->as_VMReg()->next());
reg_def Z_R1 (SOC, SOC, Op_RegI, 1, Z_R1->as_VMReg()); // v scratch2
reg_def Z_R1_H (SOC, SOC, Op_RegI, 99, Z_R1->as_VMReg()->next());
reg_def Z_R2 (SOC, SOC, Op_RegI, 2, Z_R2->as_VMReg()); // v iarg1 & iret
reg_def Z_R2_H (SOC, SOC, Op_RegI, 99, Z_R2->as_VMReg()->next());
reg_def Z_R3 (SOC, SOC, Op_RegI, 3, Z_R3->as_VMReg()); // v iarg2
reg_def Z_R3_H (SOC, SOC, Op_RegI, 99, Z_R3->as_VMReg()->next());
reg_def Z_R4 (SOC, SOC, Op_RegI, 4, Z_R4->as_VMReg()); // v iarg3
reg_def Z_R4_H (SOC, SOC, Op_RegI, 99, Z_R4->as_VMReg()->next());
reg_def Z_R5 (SOC, SOC, Op_RegI, 5, Z_R5->as_VMReg()); // v iarg4
reg_def Z_R5_H (SOC, SOC, Op_RegI, 99, Z_R5->as_VMReg()->next());
reg_def Z_R6 (SOC, SOE, Op_RegI, 6, Z_R6->as_VMReg()); // v iarg5
reg_def Z_R6_H (SOC, SOE, Op_RegI, 99, Z_R6->as_VMReg()->next());
reg_def Z_R7 (SOC, SOE, Op_RegI, 7, Z_R7->as_VMReg());
reg_def Z_R7_H (SOC, SOE, Op_RegI, 99, Z_R7->as_VMReg()->next());
reg_def Z_R8 (SOC, SOE, Op_RegI, 8, Z_R8->as_VMReg());
reg_def Z_R8_H (SOC, SOE, Op_RegI, 99, Z_R8->as_VMReg()->next());
reg_def Z_R9 (SOC, SOE, Op_RegI, 9, Z_R9->as_VMReg());
reg_def Z_R9_H (SOC, SOE, Op_RegI, 99, Z_R9->as_VMReg()->next());
reg_def Z_R10 (SOC, SOE, Op_RegI, 10, Z_R10->as_VMReg());
reg_def Z_R10_H(SOC, SOE, Op_RegI, 99, Z_R10->as_VMReg()->next());
reg_def Z_R11 (SOC, SOE, Op_RegI, 11, Z_R11->as_VMReg());
reg_def Z_R11_H(SOC, SOE, Op_RegI, 99, Z_R11->as_VMReg()->next());
reg_def Z_R12 (SOC, SOE, Op_RegI, 12, Z_R12->as_VMReg());
reg_def Z_R12_H(SOC, SOE, Op_RegI, 99, Z_R12->as_VMReg()->next());
reg_def Z_R13 (SOC, SOE, Op_RegI, 13, Z_R13->as_VMReg());
reg_def Z_R13_H(SOC, SOE, Op_RegI, 99, Z_R13->as_VMReg()->next());
reg_def Z_R14 (NS, NS, Op_RegI, 14, Z_R14->as_VMReg()); // s return_pc
reg_def Z_R14_H(NS, NS, Op_RegI, 99, Z_R14->as_VMReg()->next());
reg_def Z_R15 (NS, NS, Op_RegI, 15, Z_R15->as_VMReg()); // s SP
reg_def Z_R15_H(NS, NS, Op_RegI, 99, Z_R15->as_VMReg()->next());
// Float/Double Registers
// The rules of ADL require that double registers be defined in pairs.
// Each pair must be two 32-bit values, but not necessarily a pair of
// single float registers. In each pair, ADLC-assigned register numbers
// must be adjacent, with the lower number even. Finally, when the
// CPU stores such a register pair to memory, the word associated with
// the lower ADLC-assigned number must be stored to the lower address.
// z/Architecture has 16 64-bit floating-point registers. Each can store a single
// or double precision floating-point value.
// types: v = volatile, nv = non-volatile, s = system
reg_def Z_F0 (SOC, SOC, Op_RegF, 0, Z_F0->as_VMReg()); // v farg1 & fret
reg_def Z_F0_H (SOC, SOC, Op_RegF, 99, Z_F0->as_VMReg()->next());
reg_def Z_F1 (SOC, SOC, Op_RegF, 1, Z_F1->as_VMReg());
reg_def Z_F1_H (SOC, SOC, Op_RegF, 99, Z_F1->as_VMReg()->next());
reg_def Z_F2 (SOC, SOC, Op_RegF, 2, Z_F2->as_VMReg()); // v farg2
reg_def Z_F2_H (SOC, SOC, Op_RegF, 99, Z_F2->as_VMReg()->next());
reg_def Z_F3 (SOC, SOC, Op_RegF, 3, Z_F3->as_VMReg());
reg_def Z_F3_H (SOC, SOC, Op_RegF, 99, Z_F3->as_VMReg()->next());
reg_def Z_F4 (SOC, SOC, Op_RegF, 4, Z_F4->as_VMReg()); // v farg3
reg_def Z_F4_H (SOC, SOC, Op_RegF, 99, Z_F4->as_VMReg()->next());
reg_def Z_F5 (SOC, SOC, Op_RegF, 5, Z_F5->as_VMReg());
reg_def Z_F5_H (SOC, SOC, Op_RegF, 99, Z_F5->as_VMReg()->next());
reg_def Z_F6 (SOC, SOC, Op_RegF, 6, Z_F6->as_VMReg());
reg_def Z_F6_H (SOC, SOC, Op_RegF, 99, Z_F6->as_VMReg()->next());
reg_def Z_F7 (SOC, SOC, Op_RegF, 7, Z_F7->as_VMReg());
reg_def Z_F7_H (SOC, SOC, Op_RegF, 99, Z_F7->as_VMReg()->next());
reg_def Z_F8 (SOC, SOE, Op_RegF, 8, Z_F8->as_VMReg());
reg_def Z_F8_H (SOC, SOE, Op_RegF, 99, Z_F8->as_VMReg()->next());
reg_def Z_F9 (SOC, SOE, Op_RegF, 9, Z_F9->as_VMReg());
reg_def Z_F9_H (SOC, SOE, Op_RegF, 99, Z_F9->as_VMReg()->next());
reg_def Z_F10 (SOC, SOE, Op_RegF, 10, Z_F10->as_VMReg());
reg_def Z_F10_H(SOC, SOE, Op_RegF, 99, Z_F10->as_VMReg()->next());
reg_def Z_F11 (SOC, SOE, Op_RegF, 11, Z_F11->as_VMReg());
reg_def Z_F11_H(SOC, SOE, Op_RegF, 99, Z_F11->as_VMReg()->next());
reg_def Z_F12 (SOC, SOE, Op_RegF, 12, Z_F12->as_VMReg());
reg_def Z_F12_H(SOC, SOE, Op_RegF, 99, Z_F12->as_VMReg()->next());
reg_def Z_F13 (SOC, SOE, Op_RegF, 13, Z_F13->as_VMReg());
reg_def Z_F13_H(SOC, SOE, Op_RegF, 99, Z_F13->as_VMReg()->next());
reg_def Z_F14 (SOC, SOE, Op_RegF, 14, Z_F14->as_VMReg());
reg_def Z_F14_H(SOC, SOE, Op_RegF, 99, Z_F14->as_VMReg()->next());
reg_def Z_F15 (SOC, SOE, Op_RegF, 15, Z_F15->as_VMReg());
reg_def Z_F15_H(SOC, SOE, Op_RegF, 99, Z_F15->as_VMReg()->next());
// Special Registers
// Condition Codes Flag Registers
// z/Architecture has the PSW (program status word) that contains
// (among other information) the condition code. We treat this
// part of the PSW as a condition register CR. It consists of 4
// bits. Floating point instructions influence the same condition register CR.
reg_def Z_CR(SOC, SOC, Op_RegFlags, 0, Z_CR->as_VMReg()); // volatile
// Specify priority of register selection within phases of register
// allocation. Highest priority is first. A useful heuristic is to
// give registers a low priority when they are required by machine
// instructions, and choose no-save registers before save-on-call, and
// save-on-call before save-on-entry. Registers which participate in
// fix calling sequences should come last. Registers which are used
// as pairs must fall on an even boundary.
// It's worth about 1% on SPEC geomean to get this right.
// Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
// in adGlobals_s390.hpp which defines the <register>_num values, e.g.
// Z_R3_num. Therefore, Z_R3_num may not be (and in reality is not)
// the same as Z_R3->encoding()! Furthermore, we cannot make any
// assumptions on ordering, e.g. Z_R3_num may be less than Z_R2_num.
// Additionally, the function
// static enum RC rc_class(OptoReg::Name reg)
// maps a given <register>_num value to its chunk type (except for flags)
// and its current implementation relies on chunk0 and chunk1 having a
// size of 64 each.
alloc_class chunk0(
// chunk0 contains *all* 32 integer registers halves.
// potential SOE regs
Z_R13,Z_R13_H,
Z_R12,Z_R12_H,
Z_R11,Z_R11_H,
Z_R10,Z_R10_H,
Z_R9,Z_R9_H,
Z_R8,Z_R8_H,
Z_R7,Z_R7_H,
Z_R1,Z_R1_H,
Z_R0,Z_R0_H,
// argument registers
Z_R6,Z_R6_H,
Z_R5,Z_R5_H,
Z_R4,Z_R4_H,
Z_R3,Z_R3_H,
Z_R2,Z_R2_H,
// special registers
Z_R14,Z_R14_H,
Z_R15,Z_R15_H
);
alloc_class chunk1(
// Chunk1 contains *all* 64 floating-point registers halves.
Z_F15,Z_F15_H,
Z_F14,Z_F14_H,
Z_F13,Z_F13_H,
Z_F12,Z_F12_H,
Z_F11,Z_F11_H,
Z_F10,Z_F10_H,
Z_F9,Z_F9_H,
Z_F8,Z_F8_H,
// scratch register
Z_F7,Z_F7_H,
Z_F5,Z_F5_H,
Z_F3,Z_F3_H,
Z_F1,Z_F1_H,
// argument registers
Z_F6,Z_F6_H,
Z_F4,Z_F4_H,
Z_F2,Z_F2_H,
Z_F0,Z_F0_H
);
alloc_class chunk2(
Z_CR
);
//-------Architecture Description Register Classes-----------------------
// Several register classes are automatically defined based upon
// information in this architecture description.
// 1) reg_class inline_cache_reg (as defined in frame section)
// 2) reg_class stack_slots(/* one chunk of stack-based "registers" */)
// Integer Register Classes
reg_class z_int_reg(
/*Z_R0*/ // R0
/*Z_R1*/
Z_R2,
Z_R3,
Z_R4,
Z_R5,
Z_R6,
Z_R7,
/*Z_R8,*/ // Z_thread
Z_R9,
Z_R10,
Z_R11,
Z_R12,
Z_R13
/*Z_R14*/ // return_pc
/*Z_R15*/ // SP
);
reg_class z_no_odd_int_reg(
/*Z_R0*/ // R0
/*Z_R1*/
Z_R2,
Z_R3,
Z_R4,
/*Z_R5,*/ // odd part of fix register pair
Z_R6,
Z_R7,
/*Z_R8,*/ // Z_thread
Z_R9,
Z_R10,
Z_R11,
Z_R12,
Z_R13
/*Z_R14*/ // return_pc
/*Z_R15*/ // SP
);
reg_class z_no_arg_int_reg(
/*Z_R0*/ // R0
/*Z_R1*/ // scratch
/*Z_R2*/
/*Z_R3*/
/*Z_R4*/
/*Z_R5*/
/*Z_R6*/
Z_R7,
/*Z_R8*/ // Z_thread
Z_R9,
Z_R10,
Z_R11,
Z_R12,
Z_R13
/*Z_R14*/ // return_pc
/*Z_R15*/ // SP
);
reg_class z_rarg1_int_reg(Z_R2);
reg_class z_rarg2_int_reg(Z_R3);
reg_class z_rarg3_int_reg(Z_R4);
reg_class z_rarg4_int_reg(Z_R5);
reg_class z_rarg5_int_reg(Z_R6);
// Pointer Register Classes
// 64-bit build means 64-bit pointers means hi/lo pairs.
reg_class z_rarg5_ptrN_reg(Z_R6);
reg_class z_rarg1_ptr_reg(Z_R2_H,Z_R2);
reg_class z_rarg2_ptr_reg(Z_R3_H,Z_R3);
reg_class z_rarg3_ptr_reg(Z_R4_H,Z_R4);
reg_class z_rarg4_ptr_reg(Z_R5_H,Z_R5);
reg_class z_rarg5_ptr_reg(Z_R6_H,Z_R6);
reg_class z_thread_ptr_reg(Z_R8_H,Z_R8);
reg_class z_ptr_reg(
/*Z_R0_H,Z_R0*/ // R0
/*Z_R1_H,Z_R1*/
Z_R2_H,Z_R2,
Z_R3_H,Z_R3,
Z_R4_H,Z_R4,
Z_R5_H,Z_R5,
Z_R6_H,Z_R6,
Z_R7_H,Z_R7,
/*Z_R8_H,Z_R8,*/ // Z_thread
Z_R9_H,Z_R9,
Z_R10_H,Z_R10,
Z_R11_H,Z_R11,
Z_R12_H,Z_R12,
Z_R13_H,Z_R13
/*Z_R14_H,Z_R14*/ // return_pc
/*Z_R15_H,Z_R15*/ // SP
);
reg_class z_lock_ptr_reg(
/*Z_R0_H,Z_R0*/ // R0
/*Z_R1_H,Z_R1*/
Z_R2_H,Z_R2,
Z_R3_H,Z_R3,
Z_R4_H,Z_R4,
/*Z_R5_H,Z_R5,*/
/*Z_R6_H,Z_R6,*/
Z_R7_H,Z_R7,
/*Z_R8_H,Z_R8,*/ // Z_thread
Z_R9_H,Z_R9,
Z_R10_H,Z_R10,
Z_R11_H,Z_R11,
Z_R12_H,Z_R12,
Z_R13_H,Z_R13
/*Z_R14_H,Z_R14*/ // return_pc
/*Z_R15_H,Z_R15*/ // SP
);
reg_class z_no_arg_ptr_reg(
/*Z_R0_H,Z_R0*/ // R0
/*Z_R1_H,Z_R1*/ // scratch
/*Z_R2_H,Z_R2*/
/*Z_R3_H,Z_R3*/
/*Z_R4_H,Z_R4*/
/*Z_R5_H,Z_R5*/
/*Z_R6_H,Z_R6*/
Z_R7_H, Z_R7,
/*Z_R8_H,Z_R8*/ // Z_thread
Z_R9_H,Z_R9,
Z_R10_H,Z_R10,
Z_R11_H,Z_R11,
Z_R12_H,Z_R12,
Z_R13_H,Z_R13
/*Z_R14_H,Z_R14*/ // return_pc
/*Z_R15_H,Z_R15*/ // SP
);
// Special class for storeP instructions, which can store SP or RPC to
// TLS. (Note: Do not generalize this to "any_reg". If you add
// another register, such as FP, to this mask, the allocator may try
// to put a temp in it.)
// Register class for memory access base registers,
// This class is a superset of z_ptr_reg including Z_thread.
reg_class z_memory_ptr_reg(
/*Z_R0_H,Z_R0*/ // R0
/*Z_R1_H,Z_R1*/
Z_R2_H,Z_R2,
Z_R3_H,Z_R3,
Z_R4_H,Z_R4,
Z_R5_H,Z_R5,
Z_R6_H,Z_R6,
Z_R7_H,Z_R7,
Z_R8_H,Z_R8, // Z_thread
Z_R9_H,Z_R9,
Z_R10_H,Z_R10,
Z_R11_H,Z_R11,
Z_R12_H,Z_R12,
Z_R13_H,Z_R13
/*Z_R14_H,Z_R14*/ // return_pc
/*Z_R15_H,Z_R15*/ // SP
);
// Other special pointer regs.
reg_class z_r1_regP(Z_R1_H,Z_R1);
reg_class z_r9_regP(Z_R9_H,Z_R9);
// Long Register Classes
reg_class z_rarg1_long_reg(Z_R2_H,Z_R2);
reg_class z_rarg2_long_reg(Z_R3_H,Z_R3);
reg_class z_rarg3_long_reg(Z_R4_H,Z_R4);
reg_class z_rarg4_long_reg(Z_R5_H,Z_R5);
reg_class z_rarg5_long_reg(Z_R6_H,Z_R6);
// Longs in 1 register. Aligned adjacent hi/lo pairs.
reg_class z_long_reg(
/*Z_R0_H,Z_R0*/ // R0
/*Z_R1_H,Z_R1*/
Z_R2_H,Z_R2,
Z_R3_H,Z_R3,
Z_R4_H,Z_R4,
Z_R5_H,Z_R5,
Z_R6_H,Z_R6,
Z_R7_H,Z_R7,
/*Z_R8_H,Z_R8,*/ // Z_thread
Z_R9_H,Z_R9,
Z_R10_H,Z_R10,
Z_R11_H,Z_R11,
Z_R12_H,Z_R12,
Z_R13_H,Z_R13
/*Z_R14_H,Z_R14,*/ // return_pc
/*Z_R15_H,Z_R15*/ // SP
);
// z_long_reg without even registers
reg_class z_long_odd_reg(
/*Z_R0_H,Z_R0*/ // R0
/*Z_R1_H,Z_R1*/
Z_R3_H,Z_R3,
Z_R5_H,Z_R5,
Z_R7_H,Z_R7,
Z_R9_H,Z_R9,
Z_R11_H,Z_R11,
Z_R13_H,Z_R13
/*Z_R14_H,Z_R14,*/ // return_pc
/*Z_R15_H,Z_R15*/ // SP
);
// Special Class for Condition Code Flags Register
reg_class z_condition_reg(
Z_CR
);
// Scratch register for late profiling. Callee saved.
reg_class z_rscratch2_bits64_reg(Z_R2_H, Z_R2);
// Float Register Classes
reg_class z_flt_reg(
Z_F0,
/*Z_F1,*/ // scratch
Z_F2,
Z_F3,
Z_F4,
Z_F5,
Z_F6,
Z_F7,
Z_F8,
Z_F9,
Z_F10,
Z_F11,
Z_F12,
Z_F13,
Z_F14,
Z_F15
);
reg_class z_rscratch1_flt_reg(Z_F1);
// Double precision float registers have virtual `high halves' that
// are needed by the allocator.
reg_class z_dbl_reg(
Z_F0,Z_F0_H,
/*Z_F1,Z_F1_H,*/ // scratch
Z_F2,Z_F2_H,
Z_F3,Z_F3_H,
Z_F4,Z_F4_H,
Z_F5,Z_F5_H,
Z_F6,Z_F6_H,
Z_F7,Z_F7_H,
Z_F8,Z_F8_H,
Z_F9,Z_F9_H,
Z_F10,Z_F10_H,
Z_F11,Z_F11_H,
Z_F12,Z_F12_H,
Z_F13,Z_F13_H,
Z_F14,Z_F14_H,
Z_F15,Z_F15_H
);
reg_class z_rscratch1_dbl_reg(Z_F1,Z_F1_H);
%}
//----------DEFINITION BLOCK---------------------------------------------------
// Define 'name --> value' mappings to inform the ADLC of an integer valued name.
// Current support includes integer values in the range [0, 0x7FFFFFFF].
// Format:
// int_def <name> (<int_value>, <expression>);
// Generated Code in ad_<arch>.hpp
// #define <name> (<expression>)
// // value == <int_value>
// Generated code in ad_<arch>.cpp adlc_verification()
// assert(<name> == <int_value>, "Expect (<expression>) to equal <int_value>");
//
definitions %{
// The default cost (of an ALU instruction).
int_def DEFAULT_COST ( 100, 100);
int_def DEFAULT_COST_LOW ( 80, 80);
int_def DEFAULT_COST_HIGH ( 120, 120);
int_def HUGE_COST (1000000, 1000000);
// Put an advantage on REG_MEM vs. MEM+REG_REG operations.
int_def ALU_REG_COST ( 100, DEFAULT_COST);
int_def ALU_MEMORY_COST ( 150, 150);
// Memory refs are twice as expensive as run-of-the-mill.
int_def MEMORY_REF_COST_HI ( 220, 2 * DEFAULT_COST+20);
int_def MEMORY_REF_COST ( 200, 2 * DEFAULT_COST);
int_def MEMORY_REF_COST_LO ( 180, 2 * DEFAULT_COST-20);
// Branches are even more expensive.
int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
int_def CALL_COST ( 300, DEFAULT_COST * 3);
%}
source %{
#ifdef PRODUCT
#define BLOCK_COMMENT(str)
#define BIND(label) __ bind(label)
#else
#define BLOCK_COMMENT(str) __ block_comment(str)
#define BIND(label) __ bind(label); BLOCK_COMMENT(#label ":")
#endif
#define __ _masm.
#define Z_DISP_SIZE Immediate::is_uimm12((long)opnd_array(1)->disp(ra_,this,2)) ? 4 : 6
#define Z_DISP3_SIZE 6
// Tertiary op of a LoadP or StoreP encoding.
#define REGP_OP true
// Given a register encoding, produce an Integer Register object.
static Register reg_to_register_object(int register_encoding);
// ****************************************************************************
// REQUIRED FUNCTIONALITY
// !!!!! Special hack to get all type of calls to specify the byte offset
// from the start of the call to the point where the return address
// will point.
void PhaseOutput::pd_perform_mach_node_analysis() {
}
int MachNode::pd_alignment_required() const {
return 1;
}
int MachNode::compute_padding(int current_offset) const {
return 0;
}
int MachCallStaticJavaNode::ret_addr_offset() {
if (_method) {
return 8;
} else {
return MacroAssembler::call_far_patchable_ret_addr_offset();
}
}
int MachCallDynamicJavaNode::ret_addr_offset() {
// Consider size of receiver type profiling (C2 tiers).
int profile_receiver_type_size = 0;
int vtable_index = this->_vtable_index;
if (vtable_index == -4) {
return 14 + profile_receiver_type_size;
} else {
assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
return 36 + profile_receiver_type_size;
}
}
int MachCallRuntimeNode::ret_addr_offset() {
return 12 + MacroAssembler::call_far_patchable_ret_addr_offset();
}
int MachCallNativeNode::ret_addr_offset() {
Unimplemented();
return -1;
}
// Compute padding required for nodes which need alignment
//
// The addresses of the call instructions needs to be 4-byte aligned to
// ensure that they don't span a cache line so that they are atomically patchable.
// The actual calls get emitted at different offsets within the node emitters.
// ins_alignment needs to be set to 2 which means that up to 1 nop may get inserted.
int CallStaticJavaDirect_dynTOCNode::compute_padding(int current_offset) const {
return (0 - current_offset) & 2;
}
int CallDynamicJavaDirect_dynTOCNode::compute_padding(int current_offset) const {
return (6 - current_offset) & 2;
}
int CallRuntimeDirectNode::compute_padding(int current_offset) const {
return (12 - current_offset) & 2;
}
int CallLeafDirectNode::compute_padding(int current_offset) const {
return (12 - current_offset) & 2;
}
int CallLeafNoFPDirectNode::compute_padding(int current_offset) const {
return (12 - current_offset) & 2;
}
void emit_nop(CodeBuffer &cbuf) {
C2_MacroAssembler _masm(&cbuf);
__ z_nop();
}
// Emit an interrupt that is caught by the debugger (for debugging compiler).
void emit_break(CodeBuffer &cbuf) {
C2_MacroAssembler _masm(&cbuf);
__ z_illtrap();
}
#if !defined(PRODUCT)
void MachBreakpointNode::format(PhaseRegAlloc *, outputStream *os) const {
os->print("TA");
}
#endif
void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
emit_break(cbuf);
}
uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
return MachNode::size(ra_);
}
static inline void z_emit16(CodeBuffer &cbuf, long value) {
// 32bit instructions may become sign extended.
assert(value >= 0, "unintended sign extension (int->long)");
assert(value < (1L << 16), "instruction too large");
*((unsigned short*)(cbuf.insts_end())) = (unsigned short)value;
cbuf.set_insts_end(cbuf.insts_end() + sizeof(unsigned short));
}
static inline void z_emit32(CodeBuffer &cbuf, long value) {
// 32bit instructions may become sign extended.
assert(value < (1L << 32), "instruction too large");
*((unsigned int*)(cbuf.insts_end())) = (unsigned int)value;
cbuf.set_insts_end(cbuf.insts_end() + sizeof(unsigned int));
}
static inline void z_emit48(CodeBuffer &cbuf, long value) {
// 32bit instructions may become sign extended.
assert(value >= 0, "unintended sign extension (int->long)");
assert(value < (1L << 48), "instruction too large");
value = value<<16;
memcpy(cbuf.insts_end(), (unsigned char*)&value, 6);
cbuf.set_insts_end(cbuf.insts_end() + 6);
}
static inline unsigned int z_emit_inst(CodeBuffer &cbuf, long value) {
if (value < 0) {
// There obviously has been an unintended sign extension (int->long). Revert it.
value = (long)((unsigned long)((unsigned int)value));
}
if (value < (1L << 16)) { // 2-byte instruction
z_emit16(cbuf, value);
return 2;
}
if (value < (1L << 32)) { // 4-byte instruction, might be unaligned store
z_emit32(cbuf, value);
return 4;
}
// 6-byte instruction, probably unaligned store.
z_emit48(cbuf, value);
return 6;
}
// Check effective address (at runtime) for required alignment.
static inline void z_assert_aligned(CodeBuffer &cbuf, int disp, Register index, Register base, int alignment) {
C2_MacroAssembler _masm(&cbuf);
__ z_lay(Z_R0, disp, index, base);
__ z_nill(Z_R0, alignment-1);
__ z_brc(Assembler::bcondEqual, +3);
__ z_illtrap();
}
int emit_call_reloc(C2_MacroAssembler &_masm, intptr_t entry_point, relocInfo::relocType rtype,
PhaseRegAlloc* ra_, bool is_native_call = false) {
__ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp().
address old_mark = __ inst_mark();
unsigned int start_off = __ offset();
if (is_native_call) {
ShouldNotReachHere();
}
if (rtype == relocInfo::runtime_call_w_cp_type) {
assert((__ offset() & 2) == 0, "misaligned emit_call_reloc");
address call_addr = __ call_c_opt((address)entry_point);
if (call_addr == NULL) {
Compile::current()->env()->record_out_of_memory_failure();
return -1;
}
} else {
assert(rtype == relocInfo::none || rtype == relocInfo::opt_virtual_call_type ||
rtype == relocInfo::static_call_type, "unexpected rtype");
__ relocate(rtype);
// BRASL must be prepended with a nop to identify it in the instruction stream.
__ z_nop();
__ z_brasl(Z_R14, (address)entry_point);
}
unsigned int ret_off = __ offset();
return (ret_off - start_off);
}
static int emit_call_reloc(C2_MacroAssembler &_masm, intptr_t entry_point, RelocationHolder const& rspec) {
__ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp().
address old_mark = __ inst_mark();
unsigned int start_off = __ offset();
relocInfo::relocType rtype = rspec.type();
assert(rtype == relocInfo::opt_virtual_call_type || rtype == relocInfo::static_call_type,
"unexpected rtype");
__ relocate(rspec);
__ z_nop();
__ z_brasl(Z_R14, (address)entry_point);
unsigned int ret_off = __ offset();
return (ret_off - start_off);
}
//=============================================================================
const RegMask& MachConstantBaseNode::_out_RegMask = _Z_PTR_REG_mask;
int ConstantTable::calculate_table_base_offset() const {
return 0; // absolute addressing, no offset
}
bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
ShouldNotReachHere();
}
// Even with PC-relative TOC addressing, we still need this node.
// Float loads/stores do not support PC-relative addresses.
void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
C2_MacroAssembler _masm(&cbuf);
Register Rtoc = as_Register(ra_->get_encode(this));
__ load_toc(Rtoc);
}
uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
// PCrelative TOC access.
return 6; // sizeof(LARL)
}
#if !defined(PRODUCT)
void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
Register r = as_Register(ra_->get_encode(this));
st->print("LARL %s,&constant_pool # MachConstantBaseNode", r->name());
}
#endif
//=============================================================================
#if !defined(PRODUCT)
void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
Compile* C = ra_->C;
st->print_cr("--- MachPrologNode ---");
st->print("\t");
for (int i = 0; i < OptoPrologueNops; i++) {
st->print_cr("NOP"); st->print("\t");
}
if (VerifyThread) {
st->print_cr("Verify_Thread");
st->print("\t");
}
long framesize = C->output()->frame_size_in_bytes();
int bangsize = C->output()->bang_size_in_bytes();
// Calls to C2R adapters often do not accept exceptional returns.
// We require that their callers must bang for them. But be
// careful, because some VM calls (such as call site linkage) can
// use several kilobytes of stack. But the stack safety zone should
// account for that. See bugs 4446381, 4468289, 4497237.
if (C->output()->need_stack_bang(bangsize)) {
st->print_cr("# stack bang"); st->print("\t");
}
st->print_cr("push_frame %d", (int)-framesize);
st->print("\t");
}
#endif
void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
Compile* C = ra_->C;
C2_MacroAssembler _masm(&cbuf);
__ verify_thread();
size_t framesize = C->output()->frame_size_in_bytes();
size_t bangsize = C->output()->bang_size_in_bytes();
assert(framesize % wordSize == 0, "must preserve wordSize alignment");
if (C->clinit_barrier_on_entry()) {
assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
Label L_skip_barrier;
Register klass = Z_R1_scratch;
// Notify OOP recorder (don't need the relocation)
AddressLiteral md = __ constant_metadata_address(C->method()->holder()->constant_encoding());
__ load_const_optimized(klass, md.value());
__ clinit_barrier(klass, Z_thread, &L_skip_barrier /*L_fast_path*/);
__ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub());
__ z_br(klass);
__ bind(L_skip_barrier);
}
// Calls to C2R adapters often do not accept exceptional returns.
// We require that their callers must bang for them. But be
// careful, because some VM calls (such as call site linkage) can
// use several kilobytes of stack. But the stack safety zone should
// account for that. See bugs 4446381, 4468289, 4497237.
if (C->output()->need_stack_bang(bangsize)) {
__ generate_stack_overflow_check(bangsize);
}
assert(Immediate::is_uimm32((long)framesize), "to do: choose suitable types!");
__ save_return_pc();
// The z/Architecture abi is already accounted for in `framesize' via the
// 'out_preserve_stack_slots' declaration.
__ push_frame((unsigned int)framesize/*includes JIT ABI*/);
if (C->has_mach_constant_base_node()) {
// NOTE: We set the table base offset here because users might be
// emitted before MachConstantBaseNode.
ConstantTable& constant_table = C->output()->constant_table();
constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
}
}
uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
// Variable size. Determine dynamically.
return MachNode::size(ra_);
}
int MachPrologNode::reloc() const {
// Return number of relocatable values contained in this instruction.
return 1; // One reloc entry for load_const(toc).
}
//=============================================================================
#if !defined(PRODUCT)
void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
os->print_cr("epilog");
os->print("\t");
if (do_polling() && ra_->C->is_method_compilation()) {
os->print_cr("load_from_polling_page Z_R1_scratch");
os->print("\t");
}
}
#endif
void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
C2_MacroAssembler _masm(&cbuf);
Compile* C = ra_->C;
__ verify_thread();
// If this does safepoint polling, then do it here.
bool need_polling = do_polling() && C->is_method_compilation();
// Pop frame, restore return_pc, and all stuff needed by interpreter.
int frame_size_in_bytes = Assembler::align((C->output()->frame_slots() << LogBytesPerInt), frame::alignment_in_bytes);
__ pop_frame_restore_retPC(frame_size_in_bytes);
if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
__ reserved_stack_check(Z_R14);
}
// Touch the polling page.
if (need_polling) {
__ z_lg(Z_R1_scratch, Address(Z_thread, JavaThread::polling_page_offset()));
// We need to mark the code position where the load from the safepoint
// polling page was emitted as relocInfo::poll_return_type here.
__ relocate(relocInfo::poll_return_type);
__ load_from_polling_page(Z_R1_scratch);
}
}
uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
// Variable size. determine dynamically.
return MachNode::size(ra_);
}
int MachEpilogNode::reloc() const {
// Return number of relocatable values contained in this instruction.
return 1; // One for load_from_polling_page.
}
const Pipeline * MachEpilogNode::pipeline() const {
return MachNode::pipeline_class();
}
//=============================================================================
// Figure out which register class each belongs in: rc_int, rc_float, rc_stack.
enum RC { rc_bad, rc_int, rc_float, rc_stack };
static enum RC rc_class(OptoReg::Name reg) {
// Return the register class for the given register. The given register
// reg is a <register>_num value, which is an index into the MachRegisterNumbers
// enumeration in adGlobals_s390.hpp.
if (reg == OptoReg::Bad) {
return rc_bad;
}
// We have 32 integer register halves, starting at index 0.
if (reg < 32) {
return rc_int;
}