--vhdl | Use the VHDL backend for code generation. This currently emits VHDL 1993 source which can be consumed by other tools. |
--verilog | Use the Verilog backend for code generation. This currently emits Verilog 2001 source which can be consumed by other tools. |
--systemverilog | |
Use the SystemVerilog backend for code generation. This currently emits SystemVerilog 2012 source which can be consumed by other tools. | |
-fclash-debug | Set the debugging mode for the compiler, exposing additional output. The available options are
Default: Note This flag exists for backwards compatibility. It is now possible to set debugging flags individually with -fclash-debug-invariants, -fclash-debug-info and -fclash-debug-count-transformations. |
-fclash-debug-invariants | |
Check invariants while debugging and print warnings / errors which may be useful, such as alterting when unexpected changes occur or when a transformation introduces free variables / shadowing. | |
-fclash-debug-info | |
Specify the information to show about individual transformations while debugging. From least to most information, these are
| |
-fclash-debug-count-transformations | |
Count the transformations that are applied and print a summary at the end of the normalization phase. |
- -fclash-debug-history[=FILENAME]
- Saves all applied rewrites into
FILENAME
, for later analysis with the clash-term tool. When no filename is given it defaults tohistory.dat
.
-fclash-debug-transformations | |
List the transformations that are to be debugged. This is given as a comma-separated list of transformations, e.g. clash -fclash-debug-transformations inlineNonRep,topLet,appProp Default: [] |
- -fclash-debug-transformations-from=N
Only print debug output from applied transformation
N
and onwards.clash -fclash-debug-transformations-from=21570
Default: 0
- -fclash-debug-transformations-limit=N
Only print debug output for
N
applied transformations.clash -fclash-debug-transformations-limit=12
Default: MAX_INT
-fclash-hdldir | Specify the directory that generated HDL is written into. For example clash -fclash-hdldir build/hdl will create a directory Default: Either |
-fclash-hdlsyn | Specify the HDL synthesis tool which will be used. Available options are
Default: |
-fclash-no-cache | |
Don't reuse previously generated output from Clash, instead generating HDL from a clean state. While this leads to longer builds, it can be useful in development. Warning Previously this flag was called Default: Cache generated HDL | |
-fclash-no-check-inaccessible-idirs | |
Check that all include directories (containing primitives) exist when running Clash. If any directory does not exist, an error is thrown. Default: Check directories | |
-fclash-clear |
Remove HDL directories before writing to them (if cache can't be used). By
default, Clash will only write to non-empty directories if it can prove all
files in it are generated by a previous run. This option applies to directories
of the various top entities, i.e., the subdirectories made in the directory passed
in with
Default: Clean before build |
-fclash-no-prim-warn | |
Disable warnings for primitives that are annotated with {-# ANN f (warnAlways "This primitive is dangerous") #-} will not be shown when compiling. Default: Show warnings | |
-fclash-spec-limit | |
Change the number of times a function can undergo specialization. Default: 20 | |
-fclash-inline-limit | |
Change the number of times a function Default: 20 | |
-fclash-inline-function-limit | |
Set the threshold for function size. Below this threshold functions are always inlined (if it is not recursive). Default: 15 | |
-fclash-inline-constant-limit | |
Set the threshold for constant size. Below this threshold constants are always inlined. A value of 0 inlines all constants. Default: 0 | |
-fclash-evaluator-fuel-limit | |
Set the threshold for unfolding potentially non-terminating bindings in the evaluator. A value of 0 only unfolds terminating bindings. Default: 20 | |
-fclash-intwidth | |
Set the bit width for the Default: Machine word size ( | |
-fclash-error-extra | |
Print additional information with compiler errors if it as available. If there is extra information and this flag is not enabled, a message will be printed suggesting this flag. Default: False | |
-fclash-float-support | |
Enable support for floating point numbers. If this is disabled, Clash will not attempt to convert Float and Double values for hardware. Default: False | |
-fclash-component-prefix | |
Prefix the names of generated HDl components with a string. For example a
component clash -fclash-component-prefix "xcorp" Default: "" | |
-fclash-old-inline-strategy | |
The new inlining strategy for Clash inlines all functions which are not
marked with Default: False | |
-fclash-no-escaped-identifiers | |
Disable extended identifiers, as used in some HDLs like VHDL to allow more flexibility with names. Clash will only generate basic identifiers if this is used. Default: Escaped identifiers are allowed | |
-fclash-lower-case-basic-identifiers | |
Clash will only generate lower case basic identifiers if this is used. This affects places where the various HDLs only allow basic identifiers to be used, most notably module and file names. Default: Disabled | |
-fclash-compile-ultra | |
Aggressively run the normalizer, potentially gaining much better runtime performance at the expense of compile time. Default: False |
- -fclash-force-undefined{,0,1}
Set the value to use when an undefined value is inserted into generated HDL. This flag can be suffixed with either 0 or 1 to force use of that bit, or left without a suffix to use a HDL-specific default (e.g.
x
in Verilog).Default: Disabled
-fclash-aggressive-x-optimization | |
Remove all undefined branches from case expressions, replacing them with
another defined value in the expression. If only one branch is defined, the
case expression is elided completely. If no branches are defined the entire
expression is replaced with a call to Implies: Default: False | |
-fclash-aggressive-x-optimization-blackboxes | |
Allow blackboxes to detect undefined values and change their behavior
accordingly. For example, if Default: False | |
-fclash-edalize | |
Generate metadata for use with Edalize. This generates edam.py files in all top entities with the configuration for building that entity. Users still need to edit this file to specify the EDA tool to use, and if necessary the device to target (for Quartus, Vivado etc.) Default: False |
-main-is | When using one of --vhdl , --verilog , or --systemverilog , this
flag refers to synthesis target. For example, running Clash with
clash My.Module -main-is top --vhdl would synthesize My.Module.top . |