No testbench generated

[ggreif]

With a somewhat older clash, namely

$ ~/.cabal/bin/clash --version
CAES Language for Synchronous Hardware, version 0.6.8 (using clash-lib, version: 0.6.8)

I observed that a topEntity with a non-function signature

topEntity :: Signal (SFixed 2 10)

will not get a testbench generated even if I have

expectedOutput :: Signal (SFixed 2 10) -> Signal Bool
expectedOutput = outputVerifier $(v ...)

available. I tricked it into submission by giving topEntity a dummy input signal, but ignoring it:

topEntity :: Signal Bool -> Signal (SFixed 2 10)
topEntity _ = ... as before ...

For

CAES Language for Synchronous Hardware, version 0.6.15 (using clash-lib, version
: 0.6.13)

this trick does not work any more. What can I do?

[ggreif]

I ended up always inputting a False signal and using mux. But this is not very satisfactory :-(

[christiaanb]

Test benches will now also be generated for circuits that have no inputs. I'll release a new version of clash containing this feature today.