Generates VHDL with incorrect bit width assignment

[kfish]

Clash generates the following VHDL for some intermediate SFixed calculations.

  signal app_arg_1_app_arg  : signed(128 downto 0);
...
begin
  
  app_arg_1_app_arg <= signed'(x"000000000000000020000000000000000");

This fails in the Vivado 2015 simulator due to the width mismatch between the signal declaration (129 bits) and the literal assignment from 132 bits.

Modifying the generated code eg.

   signal app_arg_1_app_arg  : signed(128 downto 0);
   signal app_arg_1_app_arg_tmp  : signed(131 downto 0);
begin
  app_arg_1_app_arg_tmp <= signed'(x"000000000000000020000000000000000");
  app_arg_1_app_arg <=  app_arg_1_app_arg_tmp(128 downto 0);

simulates correctly.